SoC.scala (16ae9ddcda54fc9a2fddffad73174cf793ac7814) SoC.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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95 NumIRSrc: Int = 256,
96 UseXSNoCTop: Boolean = false,
97 UseXSNoCDiffTop: Boolean = false,
98 UseXSTileDiffTop: Boolean = false,
99 IMSICUseTL: Boolean = false,
100 SeperateTLBus: Boolean = false,
101 SeperateDM: Boolean = false, // for non-XSNoCTop only, should work with SeperateTLBus
102 SeperateTLBusRanges: Seq[AddressSet] = Seq(),
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 86 unchanged lines hidden (view full) ---

95 NumIRSrc: Int = 256,
96 UseXSNoCTop: Boolean = false,
97 UseXSNoCDiffTop: Boolean = false,
98 UseXSTileDiffTop: Boolean = false,
99 IMSICUseTL: Boolean = false,
100 SeperateTLBus: Boolean = false,
101 SeperateDM: Boolean = false, // for non-XSNoCTop only, should work with SeperateTLBus
102 SeperateTLBusRanges: Seq[AddressSet] = Seq(),
103 IMSICBusType: device.IMSICBusType.Value = device.IMSICBusType.AXI,
104 IMSICParams: aia.IMSICParams = aia.IMSICParams(
105 imsicIntSrcWidth = 8,
106 mAddr = 0x3A800000,
107 sgAddr = 0x3B000000,
108 geilen = 5,
109 vgeinWidth = 6,
110 iselectWidth = 12,
111 EnableImsicAsyncBridge = true,
112 HasTEEIMSIC = false
113 ),
103 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
104 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
105 SeperateTLAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
106 WFIClockGate: Boolean = false,
107 EnablePowerDown: Boolean = false
108){
109 require(
110 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,

--- 472 unchanged lines hidden --- 		114 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
115 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
116 SeperateTLAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
117 WFIClockGate: Boolean = false,
118 EnablePowerDown: Boolean = false
119){
120 require(
121 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,

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