1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package system 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt} 23import freechips.rocketchip.amba.axi4._ 24import freechips.rocketchip.devices.debug.DebugModuleKey 25import freechips.rocketchip.devices.tilelink._ 26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes} 27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} 28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} 29import freechips.rocketchip.tilelink._ 30import freechips.rocketchip.util.AsyncQueueParams 31import huancun._ 32import top.BusPerfMonitor 33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst} 35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey} 36import coupledL2.{EnableCHI, L2Param} 37import coupledL2.tl2chi.CHIIssue 38import openLLC.OpenLLCParam 39 40case object SoCParamsKey extends Field[SoCParameters] 41case object CVMParamskey extends Field[CVMParameters] 42 43case class CVMParameters 44( 45 MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff), 46 KeyIDBits: Int = 0, 47 MemencPipes: Int = 4, 48 HasMEMencryption: Boolean = false, 49 HasDelayNoencryption: Boolean = false, // Test specific 50) 51 52case class SoCParameters 53( 54 EnableILA: Boolean = false, 55 PAddrBits: Int = 48, 56 PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)), 57 PMAConfigs: Seq[PMAConfigEntry] = Seq( 58 PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3), 59 PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true), 60 PMAConfigEntry(0x80000000L, a = 1, w = true, r = true), 61 PMAConfigEntry(0x3A000000L, a = 1), 62 PMAConfigEntry(0x39002000L, a = 1, w = true, r = true), 63 PMAConfigEntry(0x39000000L, a = 1, w = true, r = true), 64 PMAConfigEntry(0x38022000L, a = 1, w = true, r = true), 65 PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true), 66 PMAConfigEntry(0x38020000L, a = 1, w = true, r = true), 67 PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable? 68 PMAConfigEntry(0x30010000L, a = 1, w = true, r = true), 69 PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true), 70 PMAConfigEntry(0x10000000L, a = 1, w = true, r = true), 71 PMAConfigEntry(0) 72 ), 73 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1), 74 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff), 75 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1), 76 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff), 77 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO 78 extIntrs: Int = 64, 79 L3NBanks: Int = 4, 80 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 81 name = "L3", 82 level = 3, 83 ways = 8, 84 sets = 2048 // 1MB per bank 85 )), 86 OpenLLCParamsOpt: Option[OpenLLCParam] = None, 87 XSTopPrefix: Option[String] = None, 88 NodeIDWidthList: Map[String, Int] = Map( 89 "B" -> 7, 90 "C" -> 9, 91 "E.b" -> 11 92 ), 93 NumHart: Int = 64, 94 NumIRFiles: Int = 7, 95 NumIRSrc: Int = 256, 96 UseXSNoCTop: Boolean = false, 97 UseXSNoCDiffTop: Boolean = false, 98 UseXSTileDiffTop: Boolean = false, 99 IMSICUseTL: Boolean = false, 100 SeperateTLBus: Boolean = false, 101 SeperateDM: Boolean = false, // for non-XSNoCTop only, should work with SeperateTLBus 102 SeperateTLBusRanges: Seq[AddressSet] = Seq(), 103 IMSICBusType: device.IMSICBusType.Value = device.IMSICBusType.AXI, 104 IMSICParams: aia.IMSICParams = aia.IMSICParams( 105 imsicIntSrcWidth = 8, 106 mAddr = 0x3A800000, 107 sgAddr = 0x3B000000, 108 geilen = 5, 109 vgeinWidth = 6, 110 iselectWidth = 12, 111 EnableImsicAsyncBridge = true, 112 HasTEEIMSIC = false 113 ), 114 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)), 115 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 116 SeperateTLAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 117 WFIClockGate: Boolean = false, 118 EnablePowerDown: Boolean = false 119){ 120 require( 121 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty, 122 "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined" 123 ) 124 // L3 configurations 125 val L3InnerBusWidth = 256 126 val L3BlockSize = 64 127 // on chip network configurations 128 val L3OuterBusWidth = 256 129 val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf) 130} 131 132trait HasSoCParameter { 133 implicit val p: Parameters 134 135 val soc = p(SoCParamsKey) 136 val cvm = p(CVMParamskey) 137 val debugOpts = p(DebugOptionsKey) 138 val tiles = p(XSTileKey) 139 val enableCHI = p(EnableCHI) 140 val issue = p(CHIIssue) 141 142 val NumCores = tiles.size 143 val EnableILA = soc.EnableILA 144 145 // Parameters for trace extension 146 val TraceTraceGroupNum = tiles.head.traceParams.TraceGroupNum 147 val TraceCauseWidth = tiles.head.XLEN 148 val TraceTvalWidth = tiles.head.traceParams.IaddrWidth 149 val TracePrivWidth = tiles.head.traceParams.PrivWidth 150 val TraceIaddrWidth = tiles.head.traceParams.IaddrWidth 151 val TraceItypeWidth = tiles.head.traceParams.ItypeWidth 152 val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2 + 1) 153 val TraceIlastsizeWidth = tiles.head.traceParams.IlastsizeWidth 154 155 // L3 configurations 156 val L3InnerBusWidth = soc.L3InnerBusWidth 157 val L3BlockSize = soc.L3BlockSize 158 val L3NBanks = soc.L3NBanks 159 160 // on chip network configurations 161 val L3OuterBusWidth = soc.L3OuterBusWidth 162 163 val NrExtIntr = soc.extIntrs 164 165 val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles 166 167 val NumIRSrc = soc.NumIRSrc 168 169 val SeperateDM = soc.SeperateDM 170 val SeperateTLBus = soc.SeperateTLBus 171 val SeperateTLBusRanges = soc.SeperateTLBusRanges 172 173 val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined) 174 soc.EnableCHIAsyncBridge else None 175 val EnableClintAsyncBridge = soc.EnableClintAsyncBridge 176 val SeperateTLAsyncBridge = if (SeperateTLBus && soc.SeperateTLAsyncBridge.isDefined) 177 soc.SeperateTLAsyncBridge else None 178 179 // seperate TL bus 180 val EnableSeperateTLAsync = SeperateTLAsyncBridge.isDefined 181 182 val WFIClockGate = soc.WFIClockGate 183 val EnablePowerDown = soc.EnablePowerDown 184 185 def HasMEMencryption = cvm.HasMEMencryption 186 require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)), 187 "HasMEMencryption most set with KeyIDBits > 0") 188} 189 190trait HasPeripheralRanges { 191 implicit val p: Parameters 192 193 private def cvm = p(CVMParamskey) 194 private def soc = p(SoCParamsKey) 195 private def dm = p(DebugModuleKey) 196 private def pmParams = p(PMParameKey) 197 198 private def mmpma = pmParams.mmpma 199 200 def onChipPeripheralRanges: Map[String, AddressSet] = Map( 201 "CLINT" -> soc.CLINTRange, 202 "BEU" -> soc.BEURange, 203 "PLIC" -> soc.PLICRange, 204 "PLL" -> soc.PLLRange, 205 "UART" -> soc.UARTLiteRange, 206 "DEBUG" -> dm.get.address, 207 "MMPMA" -> AddressSet(mmpma.address, mmpma.mask) 208 ) ++ ( 209 if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false)) 210 Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff)) 211 else 212 Map() 213 ) ++ ( 214 if (cvm.HasMEMencryption) 215 Map("MEMENC" -> cvm.MEMENCRange) 216 else 217 Map() 218 ) 219 220 def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) => 221 acc.flatMap(_.subtract(x)) 222 } 223} 224 225class ILABundle extends Bundle {} 226 227 228abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges { 229 val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize)) 230 val peripheralXbar = Option.when(!enableCHI)(TLXbar()) 231 val l3_xbar = Option.when(!enableCHI)(TLXbar()) 232 val l3_banked_xbar = Option.when(!enableCHI)(TLXbar()) 233 234 val soc_xbar = Option.when(enableCHI)(AXI4Xbar()) 235} 236 237// We adapt the following three traits from rocket-chip. 238// Source: rocket-chip/src/main/scala/subsystem/Ports.scala 239trait HaveSlaveAXI4Port { 240 this: BaseSoC => 241 242 val idBits = 14 243 244 val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters( 245 Seq(AXI4MasterParameters( 246 name = "dma", 247 id = IdRange(0, 1 << idBits) 248 )) 249 ))) 250 251 if (l3_xbar.isDefined) { 252 val errorDevice = LazyModule(new TLError( 253 params = DevNullParams( 254 address = Seq(AddressSet(0x0, 0x7fffffffL)), 255 maxAtomic = 8, 256 maxTransfer = 64), 257 beatBytes = L3InnerBusWidth / 8 258 )) 259 errorDevice.node := 260 l3_xbar.get := 261 TLFIFOFixer() := 262 TLWidthWidget(32) := 263 AXI4ToTL() := 264 AXI4UserYanker(Some(1)) := 265 AXI4Fragmenter() := 266 AXI4Buffer() := 267 AXI4Buffer() := 268 AXI4IdIndexer(1) := 269 l3FrontendAXI4Node 270 } 271 272 val dma = InModuleBody { 273 l3FrontendAXI4Node.makeIOs() 274 } 275} 276 277trait HaveAXI4MemPort { 278 this: BaseSoC => 279 val device = new MemoryDevice 280 // 48-bit physical address 281 val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL)) 282 val memAXI4SlaveNode = AXI4SlaveNode(Seq( 283 AXI4SlavePortParameters( 284 slaves = Seq( 285 AXI4SlaveParameters( 286 address = memRange, 287 regionType = RegionType.UNCACHED, 288 executable = true, 289 supportsRead = TransferSizes(1, L3BlockSize), 290 supportsWrite = TransferSizes(1, L3BlockSize), 291 interleavedId = Some(0), 292 resources = device.reg("mem") 293 ) 294 ), 295 beatBytes = L3OuterBusWidth / 8, 296 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey), 297 ) 298 )) 299 300 val mem_xbar = TLXbar() 301 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 302 val axi4mem_node = AXI4IdentityNode() 303 304 if (enableCHI) { 305 axi4mem_node := 306 soc_xbar.get 307 } else { 308 mem_xbar :=* 309 TLBuffer.chainNode(2) := 310 TLCacheCork() := 311 l3_mem_pmu := 312 TLClientsMerger() := 313 TLXbar() :=* 314 bankedNode.get 315 316 mem_xbar := 317 TLWidthWidget(8) := 318 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) := 319 peripheralXbar.get 320 321 axi4mem_node := 322 TLToAXI4() := 323 TLSourceShrinker(64) := 324 TLWidthWidget(L3OuterBusWidth / 8) := 325 TLBuffer.chainNode(2) := 326 mem_xbar 327 } 328 val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange))) 329 if (HasMEMencryption) { 330 memAXI4SlaveNode := 331 AXI4Buffer() := 332 AXI4Buffer() := 333 AXI4Buffer() := 334 AXI4IdIndexer(idBits = 14) := 335 AXI4UserYanker() := 336 axi4memencrpty.get.node 337 338 axi4memencrpty.get.node := 339 AXI4Deinterleaver(L3BlockSize) := 340 axi4mem_node 341 } else { 342 memAXI4SlaveNode := 343 AXI4Buffer() := 344 AXI4Buffer() := 345 AXI4Buffer() := 346 AXI4IdIndexer(idBits = 14) := 347 AXI4UserYanker() := 348 AXI4Deinterleaver(L3BlockSize) := 349 axi4mem_node 350 } 351 352 353 val memory = InModuleBody { 354 memAXI4SlaveNode.makeIOs() 355 } 356} 357 358trait HaveAXI4PeripheralPort { this: BaseSoC => 359 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite")) 360 val uartParams = AXI4SlaveParameters( 361 address = Seq(soc.UARTLiteRange), 362 regionType = RegionType.UNCACHED, 363 supportsRead = TransferSizes(1, 32), 364 supportsWrite = TransferSizes(1, 32), 365 resources = uartDevice.reg 366 ) 367 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters( 368 Seq(AXI4SlaveParameters( 369 address = peripheralRange, 370 regionType = RegionType.UNCACHED, 371 supportsRead = TransferSizes(1, 32), 372 supportsWrite = TransferSizes(1, 32), 373 interleavedId = Some(0) 374 ), uartParams), 375 beatBytes = 8 376 ))) 377 378 val axi4peripheral_node = AXI4IdentityNode() 379 val error_xbar = Option.when(enableCHI)(TLXbar()) 380 381 peripheralNode := 382 AXI4UserYanker() := 383 AXI4IdIndexer(idBits = 2) := 384 AXI4Buffer() := 385 AXI4Buffer() := 386 AXI4Buffer() := 387 AXI4Buffer() := 388 AXI4UserYanker() := 389 // AXI4Deinterleaver(8) := 390 axi4peripheral_node 391 392 if (enableCHI) { 393 val error = LazyModule(new TLError( 394 params = DevNullParams( 395 address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)), 396 maxAtomic = 8, 397 maxTransfer = 64), 398 beatBytes = 8 399 )) 400 error.node := error_xbar.get 401 axi4peripheral_node := 402 AXI4Deinterleaver(8) := 403 TLToAXI4() := 404 error_xbar.get := 405 TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) := 406 TLFIFOFixer() := 407 TLWidthWidget(L3OuterBusWidth / 8) := 408 AXI4ToTL() := 409 AXI4UserYanker() := 410 soc_xbar.get 411 } else { 412 axi4peripheral_node := 413 AXI4Deinterleaver(8) := 414 TLToAXI4() := 415 TLBuffer.chainNode(3) := 416 peripheralXbar.get 417 } 418 419 val peripheral = InModuleBody { 420 peripheralNode.makeIOs() 421 } 422 423} 424 425class MemMisc()(implicit p: Parameters) extends BaseSoC 426 with HaveAXI4MemPort 427 with PMAConst 428 with HaveAXI4PeripheralPort 429{ 430 431 val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 432 val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 433 434 val l3_in = TLTempNode() 435 val l3_out = TLTempNode() 436 437 val device_xbar = Option.when(enableCHI)(TLXbar()) 438 device_xbar.foreach(_ := error_xbar.get) 439 440 if (l3_banked_xbar.isDefined) { 441 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get 442 l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get 443 } 444 bankedNode match { 445 case Some(bankBinder) => 446 bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out 447 case None => 448 } 449 450 if(soc.L3CacheParamsOpt.isEmpty){ 451 l3_out :*= l3_in 452 } 453 454 if (!enableCHI) { 455 for (port <- peripheral_ports.get) { 456 peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port 457 } 458 } 459 460 core_to_l3_ports.foreach { case _ => 461 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){ 462 l3_banked_xbar.get :=* 463 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=* 464 TLBuffer() := 465 core_out 466 } 467 } 468 469 val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8)) 470 if (enableCHI) { clint.node := device_xbar.get } 471 else { clint.node := peripheralXbar.get } 472 473 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule { 474 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1)) 475 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 476 val in = IO(Input(Vec(num, Bool()))) 477 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i } 478 } 479 lazy val module = new IntSourceNodeToModuleImp(this) 480 } 481 482 val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8)) 483 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr)) 484 485 plic.intnode := plicSource.sourceNode 486 if (enableCHI) { plic.node := device_xbar.get } 487 else { plic.node := peripheralXbar.get } 488 489 val pll_node = TLRegisterNode( 490 address = Seq(soc.PLLRange), 491 device = new SimpleDevice("pll_ctrl", Seq()), 492 beatBytes = 8, 493 concurrency = 1 494 ) 495 if (enableCHI) { pll_node := device_xbar.get } 496 else { pll_node := peripheralXbar.get } 497 498 val debugModule = LazyModule(new DebugModule(NumCores)(p)) 499 val debugModuleXbarOpt = Option.when(SeperateDM)(TLXbar()) 500 if (enableCHI) { 501 if (SeperateDM) { 502 debugModule.debug.node := debugModuleXbarOpt.get 503 } else { 504 debugModule.debug.node := device_xbar.get 505 } 506 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 507 error_xbar.get := sb2tl.node 508 } 509 } else { 510 if (SeperateDM) { 511 debugModule.debug.node := debugModuleXbarOpt.get 512 } else { 513 debugModule.debug.node := peripheralXbar.get 514 } 515 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 516 l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node 517 } 518 } 519 520 val pma = LazyModule(new TLPMA) 521 if (enableCHI) { 522 pma.node := TLBuffer.chainNode(4) := device_xbar.get 523 if (HasMEMencryption) { 524 axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get 525 } 526 } else { 527 pma.node := TLBuffer.chainNode(4) := peripheralXbar.get 528 if (HasMEMencryption) { 529 axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get 530 } 531 } 532 533 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 534 535 val debug_module_io = IO(new debugModule.DebugModuleIO) 536 val ext_intrs = IO(Input(UInt(NrExtIntr.W))) 537 val rtc_clock = IO(Input(Bool())) 538 val pll0_lock = IO(Input(Bool())) 539 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W)))) 540 val cacheable_check = IO(new TLPMAIO) 541 val clintTime = IO(Output(ValidIO(UInt(64.W)))) 542 543 debugModule.module.io <> debug_module_io 544 545 // sync external interrupts 546 require(plicSource.module.in.length == ext_intrs.getWidth) 547 for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) { 548 val ext_intr_sync = RegInit(0.U(3.W)) 549 ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt) 550 plic_in := ext_intr_sync(2) 551 } 552 553 pma.module.io <> cacheable_check 554 555 if (HasMEMencryption) { 556 val cnt = Counter(true.B, 8)._1 557 axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool 558 axi4memencrpty.get.module.io.random_data := cnt(0).asBool 559 } 560 // positive edge sampling of the lower-speed rtc_clock 561 val rtcTick = RegInit(0.U(3.W)) 562 rtcTick := Cat(rtcTick(1, 0), rtc_clock) 563 clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2) 564 565 val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) } 566 val pll_lock = RegNext(next = pll0_lock, init = false.B) 567 568 clintTime := clint.module.io.time 569 570 pll0_ctrl <> VecInit(pll_ctrl_regs) 571 572 pll_node.regmap( 573 0x000 -> RegFieldGroup( 574 "Pll", Some("PLL ctrl regs"), 575 pll_ctrl_regs.zipWithIndex.map{ 576 case (r, i) => RegField(32, r, RegFieldDesc( 577 s"PLL_ctrl_$i", 578 desc = s"PLL ctrl register #$i" 579 )) 580 } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc( 581 "PLL_lock", 582 "PLL lock register" 583 )) 584 ) 585 ) 586 } 587 588 lazy val module = new SoCMiscImp(this) 589} 590 591class SoCMisc()(implicit p: Parameters) extends MemMisc 592 with HaveSlaveAXI4Port 593 594