SoC.scala (175bcfe9ae63c4f6c46e0386e26656f6fa9fe4d3) SoC.scala (05f23f575dc9b9d5ecb9f7884862bbe593024bf4)
1package system
2
3import chipsalliance.rocketchip.config.{Field, Parameters}
4import chisel3._
5import chisel3.util._
6import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
7import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
8
9case object SoCParamsKey extends Field[SoCParameters]
10
11case class SoCParameters
12(
13 cores: List[XSCoreParameters],
14 EnableILA: Boolean = false,
15 extIntrs: Int = 150,
1package system
2
3import chipsalliance.rocketchip.config.{Field, Parameters}
4import chisel3._
5import chisel3.util._
6import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
7import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
8
9case object SoCParamsKey extends Field[SoCParameters]
10
11case class SoCParameters
12(
13 cores: List[XSCoreParameters],
14 EnableILA: Boolean = false,
15 extIntrs: Int = 150,
16 useFakeL3Cache: Boolean = false
16 useFakeL3Cache: Boolean = false,
17 L3Size: Int = 4 * 1024 * 1024 // 4MB
17){
18 val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
19 // L3 configurations
20 val L3InnerBusWidth = 256
18){
19 val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
20 // L3 configurations
21 val L3InnerBusWidth = 256
21 val L3Size = 4 * 1024 * 1024 // 4MB
22 val L3BlockSize = 64
23 val L3NBanks = 4
24 val L3NWays = 8
25
26 // on chip network configurations
27 val L3OuterBusWidth = 256
28
29}

--- 50 unchanged lines hidden --- 		22 val L3BlockSize = 64
23 val L3NBanks = 4
24 val L3NWays = 8
25
26 // on chip network configurations
27 val L3OuterBusWidth = 256
28
29}

--- 50 unchanged lines hidden ---