SoC.scala (4b40434cb8e9fec610aad0fda0e437863b2716ec) SoC.scala (78a8cd257caa1ff2b977d80082b1b3a2fa98a1d3)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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58}
59
60trait HasSoCParameter {
61 implicit val p: Parameters
62
63 val soc = p(SoCParamsKey)
64 val debugOpts = p(DebugOptionsKey)
65 val tiles = p(XSTileKey)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 49 unchanged lines hidden (view full) ---

58}
59
60trait HasSoCParameter {
61 implicit val p: Parameters
62
63 val soc = p(SoCParamsKey)
64 val debugOpts = p(DebugOptionsKey)
65 val tiles = p(XSTileKey)
66 val enableCHI = p(EnableCHI)
66
67 val NumCores = tiles.size
68 val EnableILA = soc.EnableILA
69
70 // L3 configurations
71 val L3InnerBusWidth = soc.L3InnerBusWidth
72 val L3BlockSize = soc.L3BlockSize
73 val L3NBanks = soc.L3NBanks
74
75 // on chip network configurations
76 val L3OuterBusWidth = soc.L3OuterBusWidth
77
78 val NrExtIntr = soc.extIntrs
79}
80
81class ILABundle extends Bundle {}
82
83
84abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
67
68 val NumCores = tiles.size
69 val EnableILA = soc.EnableILA
70
71 // L3 configurations
72 val L3InnerBusWidth = soc.L3InnerBusWidth
73 val L3BlockSize = soc.L3BlockSize
74 val L3NBanks = soc.L3NBanks
75
76 // on chip network configurations
77 val L3OuterBusWidth = soc.L3OuterBusWidth
78
79 val NrExtIntr = soc.extIntrs
80}
81
82class ILABundle extends Bundle {}
83
84
85abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
85 val bankedNode = BankBinder(L3NBanks, L3BlockSize)
86 val peripheralXbar = TLXbar()
86 val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
87 val peripheralXbar = Option.when(!enableCHI)(TLXbar())
87 val l3_xbar = TLXbar()
88 val l3_banked_xbar = TLXbar()
88 val l3_xbar = TLXbar()
89 val l3_banked_xbar = TLXbar()
90
91 val soc_xbar = AXI4Xbar()
89}
90
91// We adapt the following three traits from rocket-chip.
92// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
93trait HaveSlaveAXI4Port {
94 this: BaseSoC =>
95
96 val idBits = 14

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146 )
147 ),
148 beatBytes = L3OuterBusWidth / 8,
149 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
150 )
151 ))
152
153 val mem_xbar = TLXbar()
92}
93
94// We adapt the following three traits from rocket-chip.
95// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
96trait HaveSlaveAXI4Port {
97 this: BaseSoC =>
98
99 val idBits = 14

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149 )
150 ),
151 beatBytes = L3OuterBusWidth / 8,
152 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
153 )
154 ))
155
156 val mem_xbar = TLXbar()
154 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform, stat_latency = true)
155 mem_xbar :=*
156 TLBuffer.chainNode(2) :=
157 TLCacheCork() :=
158 l3_mem_pmu :=
159 TLClientsMerger() :=
160 TLXbar() :=*
161 bankedNode
157 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
158 val axi4mem_node = AXI4IdentityNode()
162
159
163 mem_xbar :=
164 TLWidthWidget(8) :=
165 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
166 peripheralXbar
160 if (enableCHI) {
161 axi4mem_node :=
162 soc_xbar
163 } else {
164 mem_xbar :=*
165 TLBuffer.chainNode(2) :=
166 TLCacheCork() :=
167 l3_mem_pmu :=
168 TLClientsMerger() :=
169 TLXbar() :=*
170 bankedNode.get
167
171
172 mem_xbar :=
173 TLWidthWidget(8) :=
174 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
175 peripheralXbar.get
176
177 axi4mem_node :=
178 TLToAXI4() :=
179 TLSourceShrinker(64) :=
180 TLWidthWidget(L3OuterBusWidth / 8) :=
181 TLBuffer.chainNode(2) :=
182 mem_xbar
183 }
184
168 memAXI4SlaveNode :=
169 AXI4Buffer() :=
170 AXI4Buffer() :=
171 AXI4Buffer() :=
172 AXI4IdIndexer(idBits = 14) :=
173 AXI4UserYanker() :=
174 AXI4Deinterleaver(L3BlockSize) :=
185 memAXI4SlaveNode :=
186 AXI4Buffer() :=
187 AXI4Buffer() :=
188 AXI4Buffer() :=
189 AXI4IdIndexer(idBits = 14) :=
190 AXI4UserYanker() :=
191 AXI4Deinterleaver(L3BlockSize) :=
175 TLToAXI4() :=
176 TLSourceShrinker(64) :=
177 TLWidthWidget(L3OuterBusWidth / 8) :=
178 TLBuffer.chainNode(2) :=
179 mem_xbar
192 axi4mem_node
180
181 val memory = InModuleBody {
182 memAXI4SlaveNode.makeIOs()
183 }
184}
185
186trait HaveAXI4PeripheralPort { this: BaseSoC =>
187 // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
188 val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
193
194 val memory = InModuleBody {
195 memAXI4SlaveNode.makeIOs()
196 }
197}
198
199trait HaveAXI4PeripheralPort { this: BaseSoC =>
200 // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
201 val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
189 val uartRange = AddressSet(0x40600000, 0xf)
202 val uartRange = AddressSet(0x40600000, 0x3f)
190 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
191 val uartParams = AXI4SlaveParameters(
192 address = Seq(uartRange),
193 regionType = RegionType.UNCACHED,
203 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
204 val uartParams = AXI4SlaveParameters(
205 address = Seq(uartRange),
206 regionType = RegionType.UNCACHED,
194 supportsRead = TransferSizes(1, 8),
195 supportsWrite = TransferSizes(1, 8),
207 supportsRead = TransferSizes(1, 32),
208 supportsWrite = TransferSizes(1, 32),
196 resources = uartDevice.reg
197 )
198 val peripheralRange = AddressSet(
199 0x0, 0x7fffffff
200 ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
201 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
202 Seq(AXI4SlaveParameters(
203 address = peripheralRange,
204 regionType = RegionType.UNCACHED,
209 resources = uartDevice.reg
210 )
211 val peripheralRange = AddressSet(
212 0x0, 0x7fffffff
213 ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
214 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
215 Seq(AXI4SlaveParameters(
216 address = peripheralRange,
217 regionType = RegionType.UNCACHED,
205 supportsRead = TransferSizes(1, 8),
206 supportsWrite = TransferSizes(1, 8),
218 supportsRead = TransferSizes(1, 32),
219 supportsWrite = TransferSizes(1, 32),
207 interleavedId = Some(0)
208 ), uartParams),
209 beatBytes = 8
210 )))
220 interleavedId = Some(0)
221 ), uartParams),
222 beatBytes = 8
223 )))
224 private val error = LazyModule(new TLError(
225 params = DevNullParams(
226 address = Seq(AddressSet(0x1000000000L, 0xfffffffffL)),
227 maxAtomic = 8,
228 maxTransfer = 64),
229 beatBytes = 8
230 ))
211
231
232 val axi4peripheral_node = AXI4IdentityNode()
233 val error_xbar = TLXbar()
234
212 peripheralNode :=
213 AXI4UserYanker() :=
214 AXI4IdIndexer(idBits = 2) :=
215 AXI4Buffer() :=
216 AXI4Buffer() :=
217 AXI4Buffer() :=
218 AXI4Buffer() :=
219 AXI4UserYanker() :=
235 peripheralNode :=
236 AXI4UserYanker() :=
237 AXI4IdIndexer(idBits = 2) :=
238 AXI4Buffer() :=
239 AXI4Buffer() :=
240 AXI4Buffer() :=
241 AXI4Buffer() :=
242 AXI4UserYanker() :=
220 AXI4Deinterleaver(8) :=
221 TLToAXI4() :=
222 TLBuffer.chainNode(3) :=
223 peripheralXbar
243 // AXI4Deinterleaver(8) :=
244 axi4peripheral_node
245
246 if (enableCHI) {
247 error.node := error_xbar
248 axi4peripheral_node :=
249 AXI4Deinterleaver(8) :=
250 TLToAXI4() :=
251 error_xbar :=
252 TLFIFOFixer() :=
253 TLWidthWidget(L3OuterBusWidth / 8) :=
254 AXI4ToTL() :=
255 AXI4UserYanker() :=
256 soc_xbar
257 } else {
258 axi4peripheral_node :=
259 AXI4Deinterleaver(8) :=
260 TLToAXI4() :=
261 TLBuffer.chainNode(3) :=
262 peripheralXbar.get
263 }
224
225 val peripheral = InModuleBody {
226 peripheralNode.makeIOs()
227 }
228
229}
230
231class MemMisc()(implicit p: Parameters) extends BaseSoC
232 with HaveAXI4MemPort
233 with PMAConst
264
265 val peripheral = InModuleBody {
266 peripheralNode.makeIOs()
267 }
268
269}
270
271class MemMisc()(implicit p: Parameters) extends BaseSoC
272 with HaveAXI4MemPort
273 with PMAConst
274 with HaveAXI4PeripheralPort
234{
275{
235 val enableCHI = p(EnableCHI)
236
276
237 val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
238 val core_to_l3_ports = if (enableCHI) None else Some(Array.fill(NumCores) { TLTempNode() })
277 val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
278 val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
239
240 val l3_in = TLTempNode()
241 val l3_out = TLTempNode()
242
279
280 val l3_in = TLTempNode()
281 val l3_out = TLTempNode()
282
283 val device_xbar = TLXbar()
284 device_xbar := error_xbar
285
243 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar
286 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar
244 bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
287 bankedNode match {
288 case Some(bankBinder) =>
289 bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
290 case None =>
291 }
245
246 if(soc.L3CacheParamsOpt.isEmpty){
247 l3_out :*= l3_in
248 }
249
292
293 if(soc.L3CacheParamsOpt.isEmpty){
294 l3_out :*= l3_in
295 }
296
250 for(port <- peripheral_ports) {
251 peripheralXbar := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
297 if (!enableCHI) {
298 for (port <- peripheral_ports.get) {
299 peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
300 }
252 }
253
254 core_to_l3_ports.foreach { case _ =>
255 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
256 l3_banked_xbar :=*
257 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
258 TLBuffer() :=
259 core_out
260 }
261 }
301 }
302
303 core_to_l3_ports.foreach { case _ =>
304 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
305 l3_banked_xbar :=*
306 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
307 TLBuffer() :=
308 core_out
309 }
310 }
262 l3_banked_xbar := TLBuffer.chainNode(2) := l3_xbar
263
311
312 if (!enableCHI) {
313 l3_banked_xbar := TLBuffer.chainNode(2) := l3_xbar
314 }
315
264 val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
316 val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
265 clint.node := peripheralXbar
317 if (enableCHI) { clint.node := device_xbar }
318 else { clint.node := peripheralXbar.get }
266
267 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
268 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
269 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
270 val in = IO(Input(Vec(num, Bool())))
271 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
272 }
273 lazy val module = new IntSourceNodeToModuleImp(this)
274 }
275
276 val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
277 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
278
279 plic.intnode := plicSource.sourceNode
319
320 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
321 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
322 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
323 val in = IO(Input(Vec(num, Bool())))
324 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
325 }
326 lazy val module = new IntSourceNodeToModuleImp(this)
327 }
328
329 val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
330 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
331
332 plic.intnode := plicSource.sourceNode
280 plic.node := peripheralXbar
333 if (enableCHI) { plic.node := device_xbar }
334 else { plic.node := peripheralXbar.get }
281
282 val pll_node = TLRegisterNode(
283 address = Seq(AddressSet(0x3a000000L, 0xfff)),
284 device = new SimpleDevice("pll_ctrl", Seq()),
285 beatBytes = 8,
286 concurrency = 1
287 )
335
336 val pll_node = TLRegisterNode(
337 address = Seq(AddressSet(0x3a000000L, 0xfff)),
338 device = new SimpleDevice("pll_ctrl", Seq()),
339 beatBytes = 8,
340 concurrency = 1
341 )
288 pll_node := peripheralXbar
342 if (enableCHI) { pll_node := device_xbar }
343 else { pll_node := peripheralXbar.get }
289
290 val debugModule = LazyModule(new DebugModule(NumCores)(p))
344
345 val debugModule = LazyModule(new DebugModule(NumCores)(p))
291 debugModule.debug.node := peripheralXbar
292 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
293 l3_xbar := TLBuffer() := sb2tl.node
346 if (enableCHI) {
347 debugModule.debug.node := device_xbar
348 // TODO: l3_xbar
349 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
350 error_xbar := sb2tl.node
351 }
352 } else {
353 debugModule.debug.node := peripheralXbar.get
354 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
355 l3_xbar := TLBuffer() := sb2tl.node
356 }
294 }
295
296 val pma = LazyModule(new TLPMA)
357 }
358
359 val pma = LazyModule(new TLPMA)
297 pma.node :=
298 TLBuffer.chainNode(4) :=
299 peripheralXbar
360 if (enableCHI) {
361 pma.node := TLBuffer.chainNode(4) := device_xbar
362 } else {
363 pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
364 }
300
301 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
302
303 val debug_module_io = IO(new debugModule.DebugModuleIO)
304 val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
305 val rtc_clock = IO(Input(Bool()))
306 val pll0_lock = IO(Input(Bool()))
307 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))

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342 "PLL lock register"
343 ))
344 )
345 )
346 }
347
348 lazy val module = new SoCMiscImp(this)
349}
365
366 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
367
368 val debug_module_io = IO(new debugModule.DebugModuleIO)
369 val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
370 val rtc_clock = IO(Input(Bool()))
371 val pll0_lock = IO(Input(Bool()))
372 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))

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407 "PLL lock register"
408 ))
409 )
410 )
411 }
412
413 lazy val module = new SoCMiscImp(this)
414}
415
350class SoCMisc()(implicit p: Parameters) extends MemMisc
416class SoCMisc()(implicit p: Parameters) extends MemMisc
351 with HaveAXI4PeripheralPort
352 with HaveSlaveAXI4Port
353
417 with HaveSlaveAXI4Port
418