SoC.scala (76ed5703600ebfe9082d269507bd6f5cb9b8ffde) SoC.scala (5bd65c56355db1d4f5b92a3815df78273c01b892)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.PMAConst
35import xiangshan.{DebugOptionsKey, XSTileKey}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39import xiangshan.PMParameKey
40
41case object SoCParamsKey extends Field[SoCParameters]
42
43case class SoCParameters
44(
45 EnableILA: Boolean = false,
46 PAddrBits: Int = 48,
39
40case object SoCParamsKey extends Field[SoCParameters]
41
42case class SoCParameters
43(
44 EnableILA: Boolean = false,
45 PAddrBits: Int = 48,
47 PmemRanges: Seq[(BigInt, BigInt)] = Seq((0x80000000L, 0x80000000000L)),
46 PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
47 PMAConfigs: Seq[PMAConfigEntry] = Seq(
48 PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
49 PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
50 PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
51 PMAConfigEntry(0x3A000000L, a = 1),
52 PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
53 PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
54 PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
55 PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
56 PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
57 PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
58 PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
59 PMAConfigEntry(0)
60 ),
48 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
49 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
50 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
51 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
52 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
53 extIntrs: Int = 64,
54 L3NBanks: Int = 4,
55 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(

--- 438 unchanged lines hidden --- 		61 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
62 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
63 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
64 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
65 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
66 extIntrs: Int = 64,
67 L3NBanks: Int = 4,
68 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(

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