SoC.scala (bbe4506dea963b9c4bf6379d789e413ba6647955) SoC.scala (5c06072729ebf9577a23fe84f4eb39de6932028f)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.PMAConst
35import xiangshan.{DebugOptionsKey, XSTileKey}
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.PMAConst
35import xiangshan.{DebugOptionsKey, XSTileKey}
36import coupledL2.EnableCHI
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
38import xiangshan.PMParameKey
39
40case object SoCParamsKey extends Field[SoCParameters]
41
42case class SoCParameters
43(
44 EnableILA: Boolean = false,
45 PAddrBits: Int = 48,

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52 extIntrs: Int = 64,
53 L3NBanks: Int = 4,
54 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
55 name = "L3",
56 level = 3,
57 ways = 8,
58 sets = 2048 // 1MB per bank
59 )),
39import xiangshan.PMParameKey
40
41case object SoCParamsKey extends Field[SoCParameters]
42
43case class SoCParameters
44(
45 EnableILA: Boolean = false,
46 PAddrBits: Int = 48,

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53 extIntrs: Int = 64,
54 L3NBanks: Int = 4,
55 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
56 name = "L3",
57 level = 3,
58 ways = 8,
59 sets = 2048 // 1MB per bank
60 )),
61 OpenLLCParamsOpt: Option[OpenLLCParam] = Some(OpenLLCParam(
62 name = "LLC",
63 ways = 8,
64 sets = 2048,
65 banks = 4,
66 clientCaches = Seq(L2Param())
67 )),
60 XSTopPrefix: Option[String] = None,
61 NodeIDWidthList: Map[String, Int] = Map(
62 "B" -> 7,
63 "E.b" -> 11
64 ),
65 NumHart: Int = 64,
66 NumIRFiles: Int = 7,
67 NumIRSrc: Int = 256,

--- 408 unchanged lines hidden --- 		68 XSTopPrefix: Option[String] = None,
69 NodeIDWidthList: Map[String, Int] = Map(
70 "B" -> 7,
71 "E.b" -> 11
72 ),
73 NumHart: Int = 64,
74 NumIRFiles: Int = 7,
75 NumIRSrc: Int = 256,

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