Top.scala (2993c5ecece73b73073301e23435ca1b763d0b5f) Top.scala (78a8cd257caa1ff2b977d80082b1b3a2fa98a1d3)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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20import chisel3._
21import chisel3.util._
22import chisel3.experimental.dataview._
23import difftest.DifftestModule
24import xiangshan._
25import utils._
26import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
27import coupledL2.EnableCHI
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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20import chisel3._
21import chisel3.util._
22import chisel3.experimental.dataview._
23import difftest.DifftestModule
24import xiangshan._
25import utils._
26import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
27import coupledL2.EnableCHI
28import openLLC.DummyLLC
28import utility._
29import system._
30import device._
31import chisel3.stage.ChiselGeneratorAnnotation
32import org.chipsalliance.cde.config._
33import freechips.rocketchip.diplomacy._
34import freechips.rocketchip.tile._
35import freechips.rocketchip.tilelink._

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43{
44 // val misc = LazyModule(new SoCMisc())
45 lazy val dts = DTS(bindingTree)
46 lazy val json = JSON(bindingTree)
47}
48
49class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
50{
29import utility._
30import system._
31import device._
32import chisel3.stage.ChiselGeneratorAnnotation
33import org.chipsalliance.cde.config._
34import freechips.rocketchip.diplomacy._
35import freechips.rocketchip.tile._
36import freechips.rocketchip.tilelink._

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44{
45 // val misc = LazyModule(new SoCMisc())
46 lazy val dts = DTS(bindingTree)
47 lazy val json = JSON(bindingTree)
48}
49
50class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
51{
51 val enableCHI = p(EnableCHI)
52
53 val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
54 val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
55 val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
56
57 ResourceBinding {
58 val width = ResourceInt(2)
59 val model = "freechips,rocketchip-unknown"
60 Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
61 Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
62 Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
63 Resource(ResourceAnchors.root, "width").bind(width)
64 Resource(ResourceAnchors.soc, "width").bind(width)
65 Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
66 def bindManagers(xbar: TLNexusNode) = {
67 ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
68 manager.resources.foreach(r => r.bind(manager.toResource))
69 }
70 }
52 val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
53 val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
54 val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
55
56 ResourceBinding {
57 val width = ResourceInt(2)
58 val model = "freechips,rocketchip-unknown"
59 Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
60 Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
61 Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
62 Resource(ResourceAnchors.root, "width").bind(width)
63 Resource(ResourceAnchors.soc, "width").bind(width)
64 Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
65 def bindManagers(xbar: TLNexusNode) = {
66 ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
67 manager.resources.foreach(r => r.bind(manager.toResource))
68 }
69 }
71 bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
72 bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
70 if (!enableCHI) {
71 bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
72 bindManagers(misc.peripheralXbar.get.asInstanceOf[TLNexusNode])
73 }
73 }
74
75 println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
76
77 val core_with_l2 = tiles.map(coreParams =>
78 LazyModule(new XSTile()(p.alterPartial({
79 case XSCoreParamsKey => coreParams
80 })))

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85 case HCCacheParamsKey => l3param.copy(
86 hartIds = tiles.map(_.HartId),
87 FPGAPlatform = debugOpts.FPGAPlatform
88 )
89 case MaxHartIdBits => p(MaxHartIdBits)
90 })))
91 )
92
74 }
75
76 println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
77
78 val core_with_l2 = tiles.map(coreParams =>
79 LazyModule(new XSTile()(p.alterPartial({
80 case XSCoreParamsKey => coreParams
81 })))

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86 case HCCacheParamsKey => l3param.copy(
87 hartIds = tiles.map(_.HartId),
88 FPGAPlatform = debugOpts.FPGAPlatform
89 )
90 case MaxHartIdBits => p(MaxHartIdBits)
91 })))
92 )
93
93 // recieve all prefetch req from cores
94 val chi_dummyllc_opt = Option.when(enableCHI)(LazyModule(new DummyLLC(numRNs = NumCores)(p)))
95
96 // receive all prefetch req from cores
94 val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
95 x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
96 }
97
98 val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
99 case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
100 case None => None
101 }
102
103 for (i <- 0 until NumCores) {
104 core_with_l2(i).clint_int_node := misc.clint.intnode
105 core_with_l2(i).plic_int_node :*= misc.plic.intnode
106 core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
107 misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
108 if (!enableCHI) {
97 val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
98 x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
99 }
100
101 val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
102 case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
103 case None => None
104 }
105
106 for (i <- 0 until NumCores) {
107 core_with_l2(i).clint_int_node := misc.clint.intnode
108 core_with_l2(i).plic_int_node :*= misc.plic.intnode
109 core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
110 misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
111 if (!enableCHI) {
109 misc.peripheral_ports(i) := core_with_l2(i).tl_uncache
110 } else {
111 // Make diplomacy happy
112 val clientParameters = TLMasterPortParameters.v1(
113 clients = Seq(TLMasterParameters.v1(
114 "uncache"
115 ))
116 )
117 val clientNode = TLClientNode(Seq(clientParameters))
118 misc.peripheral_ports(i) := clientNode
112 misc.peripheral_ports.get(i) := core_with_l2(i).tl_uncache
119 }
113 }
120 misc.core_to_l3_ports.foreach(port => port(i) :=* core_with_l2(i).memory_port.get)
114 core_with_l2(i).memory_port.foreach(port => (misc.core_to_l3_ports.get)(i) :=* port)
121 memblock_pf_recv_nodes(i).map(recv => {
122 println(s"Connecting Core_${i}'s L1 pf source to L3!")
123 recv := core_with_l2(i).core_l3_pf_port.get
124 })
125 }
126
115 memblock_pf_recv_nodes(i).map(recv => {
116 println(s"Connecting Core_${i}'s L1 pf source to L3!")
117 recv := core_with_l2(i).core_l3_pf_port.get
118 })
119 }
120
127 l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
121 l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar.get))
128 l3cacheOpt.map(_.intnode.map(int => {
129 misc.plic.intnode := IntBuffer() := int
130 }))
131
132 val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
133 l3cacheOpt.get.rst_nodes.get
134 } else {
135 core_with_l2.map(_ => BundleBridgeSource(() => Reset()))

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158 for ((core, i) <- core_with_l2.zipWithIndex) {
159 println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
160 core.core_l3_tpmeta_sink_port.get := broadcast.node
161 }
162 })
163 case None =>
164 }
165
122 l3cacheOpt.map(_.intnode.map(int => {
123 misc.plic.intnode := IntBuffer() := int
124 }))
125
126 val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
127 l3cacheOpt.get.rst_nodes.get
128 } else {
129 core_with_l2.map(_ => BundleBridgeSource(() => Reset()))

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152 for ((core, i) <- core_with_l2.zipWithIndex) {
153 println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
154 core.core_l3_tpmeta_sink_port.get := broadcast.node
155 }
156 })
157 case None =>
158 }
159
160 chi_dummyllc_opt match {
161 case Some(llc) =>
162 misc.soc_xbar := llc.axi4node
163 case None =>
164 }
165
166 class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
167 soc.XSTopPrefix.foreach { prefix =>
168 val mod = this.toNamed
169 annotate(new ChiselAnnotation {
170 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
171 })
172 }
173
174 FileRegisters.add("dts", dts)
175 FileRegisters.add("graphml", graphML)
176 FileRegisters.add("json", json)
177 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
178
179 val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))
166 class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
167 soc.XSTopPrefix.foreach { prefix =>
168 val mod = this.toNamed
169 annotate(new ChiselAnnotation {
170 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
171 })
172 }
173
174 FileRegisters.add("dts", dts)
175 FileRegisters.add("graphml", graphML)
176 FileRegisters.add("json", json)
177 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
178
179 val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))
180 val peripheral = socMisc.map(m => IO(new VerilogAXI4Record(m.peripheral.elts.head.params)))
180 val peripheral = IO(new VerilogAXI4Record(m.peripheral.elts.head.params))
181 val memory = IO(new VerilogAXI4Record(misc.memory.elts.head.params))
182
183 socMisc match {
184 case Some(m) =>
185 m.dma.elements.head._2 <> dma.get.viewAs[AXI4Bundle]
181 val memory = IO(new VerilogAXI4Record(misc.memory.elts.head.params))
182
183 socMisc match {
184 case Some(m) =>
185 m.dma.elements.head._2 <> dma.get.viewAs[AXI4Bundle]
186 peripheral.get.viewAs[AXI4Bundle] <> m.peripheral.elements.head._2
187 dontTouch(dma.get)
186 dontTouch(dma.get)
188 dontTouch(peripheral.get)
189 case None =>
190 }
191
192 memory.viewAs[AXI4Bundle] <> misc.memory.elements.head._2
187 case None =>
188 }
189
190 memory.viewAs[AXI4Bundle] <> misc.memory.elements.head._2
191 peripheral.viewAs[AXI4Bundle] <> misc.peripheral.elements.head._2
193
194 val io = IO(new Bundle {
195 val clock = Input(Bool())
196 val reset = Input(AsyncReset())
197 val sram_config = Input(UInt(16.W))
198 val extIntrs = Input(UInt(NrExtIntr.W))
199 val pll0_lock = Input(Bool())
200 val pll0_ctrl = Output(Vec(6, UInt(32.W)))

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231 misc.module.cacheable_check <> io.cacheable_check
232
233 io.pll0_ctrl <> misc.module.pll0_ctrl
234
235 for ((core, i) <- core_with_l2.zipWithIndex) {
236 core.module.io.hartId := i.U
237 io.riscv_halt(i) := core.module.io.cpu_halt
238 core.module.io.reset_vector := io.riscv_rst_vec(i)
192
193 val io = IO(new Bundle {
194 val clock = Input(Bool())
195 val reset = Input(AsyncReset())
196 val sram_config = Input(UInt(16.W))
197 val extIntrs = Input(UInt(NrExtIntr.W))
198 val pll0_lock = Input(Bool())
199 val pll0_ctrl = Output(Vec(6, UInt(32.W)))

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230 misc.module.cacheable_check <> io.cacheable_check
231
232 io.pll0_ctrl <> misc.module.pll0_ctrl
233
234 for ((core, i) <- core_with_l2.zipWithIndex) {
235 core.module.io.hartId := i.U
236 io.riscv_halt(i) := core.module.io.cpu_halt
237 core.module.io.reset_vector := io.riscv_rst_vec(i)
238 chi_dummyllc_opt.foreach { case llc =>
239 llc.module.io.rn(i) <> core.module.io.chi.get
240 core.module.io.nodeID.get := i.U // TODO
241 }
239 }
240
241 if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
242 // tie off core soft reset
243 for(node <- core_rst_nodes){
244 node.out.head._1 := false.B.asAsyncReset
245 }
246 }

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259 case None =>
260 }
261 l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
262 core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
263 case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
264 }
265
266 core_with_l2.foreach { case tile =>
242 }
243
244 if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
245 // tie off core soft reset
246 for(node <- core_rst_nodes){
247 node.out.head._1 := false.B.asAsyncReset
248 }
249 }

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262 case None =>
263 }
264 l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
265 core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
266 case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
267 }
268
269 core_with_l2.foreach { case tile =>
267 tile.module.io.chi.foreach { case chi_port =>
268 chi_port <> DontCare
269 dontTouch(chi_port)
270 }
271 tile.module.io.nodeID.foreach { case nodeID =>
272 nodeID := DontCare
273 dontTouch(nodeID)
274 }
275 }
276
277 misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
278 misc.module.debug_module_io.clock := io.clock

--- 48 unchanged lines hidden --- 		270 tile.module.io.nodeID.foreach { case nodeID =>
271 nodeID := DontCare
272 dontTouch(nodeID)
273 }
274 }
275
276 misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
277 misc.module.debug_module_io.clock := io.clock

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