refactor(DFT): refactor `DFT` IO (#4530)

feat(AIA): integrate ChiselAIA again (#4509)

chore(XSNoCTop): minor connection changes (#4501)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

fix(Top): fix `l3Miss` interface connection (#4410)

feat(AIA): integrate ChiselAIA (#4378)

config: add fpga diff top on tilelink for diff_top (#4370)

In order to be compatible with st's environment, the fpga difftest
project in tilelink is generated in the same way as noc top, which leads

config: add fpga diff top on tilelink for diff_top (#4370)

In order to be compatible with st's environment, the fpga difftest
project in tilelink is generated in the same way as noc top, which leads
tilelink top and difftest signals to difftop together.

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feat(Top): remain dfx io for `XSTile` under `Top.scala` (#4351)

feat(dfx): integerate dfx components (#4312)

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

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submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/d

feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/difftest IOs.

Currently we use two-step flow for CHI-NoC-XS as follow:
Step1. Generate single-core XSNoCDiffTop with JsonProfile,
which support generate another DifftestEndpoint seperately.
Step2. Generate n-core Difftest according to JsonProfile
Step3. Connect XS and Difftest manually or by some scripts.

As XSNoCDiffTop is only part of Difftest, we collect PerfCounters
for each DiffTop, need control signals passed from Outer module.
And to avoid potential connection problem, we add checker module
and CI test.

To maintain compatibility with previous IT/ST flow, we extend
XSNoCDiffTopConfig to enable difftest wrapper.

An example usage:
make verilog PLDM=1 PLDM_ARGS="--difftest-config H" CONFIG=XSNoCDiffTopConfig

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feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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fix(device, DebugMoudle): do not use clock with Bool type (#4152)

* gsim can not handle such clocks

fix(XSTop): assign unique nodeID to each core (#4151)

Without this commit, CHI messages cannot be correctly routed in
multi-core scenarios, leading to simulation errors.

feat(DM, hartReset): support `hartReset` which could reset selected harts

* Add hartResetReq in XSNocTop.
* Support `hartReset` features

submodule(OpenLLC): add support for top-down analysis (#4113)

fix(trace): add pipe for traceCoreInterface in memblock and l2top

feat(trace): add TraceCoreInterface in top.

perf(XSTop): improve concurrency of CHI-AXI bridge (#4008)

The previous design set OpenNCB concurrency to the default value of 15.
This commit adjusts the configuration to align with the parallelis

perf(XSTop): improve concurrency of CHI-AXI bridge (#4008)

The previous design set OpenNCB concurrency to the default value of 15.
This commit adjusts the configuration to align with the parallelism of
L2 MSHR requests and MMIO requests, enhancing overall performance.

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feat(dbltrp) : add support for critical error (#3793)

feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)

* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and O

feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)

* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and OpenLLC
* Update build dependencies and submodule initialization rules

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fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)