| Top.scala (42cb64260d34f2b47839d26c7af8b31eef9031c9) | Top.scala (8cfc24b28454f1915c339ce79485711f8e438f59) |
|---|---|
| 1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: --- 307 unchanged lines hidden (view full) --- 316 dontTouch(memory) 317 misc.module.ext_intrs := io.extIntrs 318 misc.module.rtc_clock := io.rtc_clock 319 misc.module.pll0_lock := io.pll0_lock 320 misc.module.cacheable_check <> io.cacheable_check 321 322 io.pll0_ctrl <> misc.module.pll0_ctrl 323 | 1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: --- 307 unchanged lines hidden (view full) --- 316 dontTouch(memory) 317 misc.module.ext_intrs := io.extIntrs 318 misc.module.rtc_clock := io.rtc_clock 319 misc.module.pll0_lock := io.pll0_lock 320 misc.module.cacheable_check <> io.cacheable_check 321 322 io.pll0_ctrl <> misc.module.pll0_ctrl 323 |
| 324 val msiInfo = WireInit(0.U.asTypeOf(ValidIO(new MsiInfoBundle))) | 324 val msiInfo = WireInit(0.U.asTypeOf(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))) |
| 325 326 327 for ((core, i) <- core_with_l2.zipWithIndex) { 328 core.module.io.hartId := i.U 329 core.module.io.msiInfo := msiInfo 330 core.module.io.clintTime := misc.module.clintTime 331 io.riscv_halt(i) := core.module.io.cpu_halt 332 io.riscv_critical_error(i) := core.module.io.cpu_crtical_error --- 179 unchanged lines hidden --- | 325 326 327 for ((core, i) <- core_with_l2.zipWithIndex) { 328 core.module.io.hartId := i.U 329 core.module.io.msiInfo := msiInfo 330 core.module.io.clintTime := misc.module.clintTime 331 io.riscv_halt(i) := core.module.io.cpu_halt 332 io.riscv_critical_error(i) := core.module.io.cpu_crtical_error --- 179 unchanged lines hidden --- |