| Top.scala (7f37d55fc418d3b4583220e634da7e459802c6d8) | Top.scala (51e45dbbf87325e45ff2af6ca86ed6c7eed04464) |
|---|---|
| 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 228 unchanged lines hidden (view full) --- 237 } 238 239 } 240 241 lazy val module = new XSTopImp(this) 242} 243 244object TopMain extends App { | 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 228 unchanged lines hidden (view full) --- 237 } 238 239 } 240 241 lazy val module = new XSTopImp(this) 242} 243 244object TopMain extends App { |
| 245 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) | 245 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) |
| 246 247 // tools: init to close dpi-c when in fpga 248 val envInFPGA = config(DebugOptionsKey).FPGAPlatform 249 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB 250 val enableConstantin = config(DebugOptionsKey).EnableConstantin 251 Constantin.init(enableConstantin && !envInFPGA) 252 ChiselDB.init(enableChiselDB && !envInFPGA) 253 254 val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) | 246 247 // tools: init to close dpi-c when in fpga 248 val envInFPGA = config(DebugOptionsKey).FPGAPlatform 249 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB 250 val enableConstantin = config(DebugOptionsKey).EnableConstantin 251 Constantin.init(enableConstantin && !envInFPGA) 252 ChiselDB.init(enableChiselDB && !envInFPGA) 253 254 val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) |
| 255 Generator.execute(firrtlOpts, soc.module, firrtlComplier, firtoolOpts) | 255 Generator.execute(firrtlOpts, soc.module, firtoolOpts) |
| 256 FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.") 257} | 256 FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.") 257} |