| L2Top.scala (0e28018481fa4b29a9d6aa8cedfb51cad5dca421) | L2Top.scala (78a8cd257caa1ff2b977d80082b1b3a2fa98a1d3) |
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| 1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 --- 51 unchanged lines hidden (view full) --- 60 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 61 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 62 buffers.zipWithIndex.foreach{ case (b, i) => { 63 b.suggestName(s"${n}_${i}") 64 }} 65 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 66 (buffers, node) 67 } | 1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 --- 51 unchanged lines hidden (view full) --- 60 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 61 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 62 buffers.zipWithIndex.foreach{ case (b, i) => { 63 b.suggestName(s"${n}_${i}") 64 }} 65 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 66 (buffers, node) 67 } |
| 68 val enableCHI = p(EnableCHI) | |
| 69 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 70 // =========== Components ============ 71 val l1_xbar = TLXbar() 72 val mmio_xbar = TLXbar() 73 val mmio_port = TLIdentityNode() // to L3 74 val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode()) 75 val beu = LazyModule(new BusErrorUnit( 76 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 77 )) 78 79 val i_mmio_port = TLTempNode() 80 val d_mmio_port = TLTempNode() 81 82 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW | 68 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 69 // =========== Components ============ 70 val l1_xbar = TLXbar() 71 val mmio_xbar = TLXbar() 72 val mmio_port = TLIdentityNode() // to L3 73 val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode()) 74 val beu = LazyModule(new BusErrorUnit( 75 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 76 )) 77 78 val i_mmio_port = TLTempNode() 79 val d_mmio_port = TLTempNode() 80 81 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW |
| 83 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform, stat_latency = true) | 82 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) |
| 84 val xbar_l2_buffer = TLBuffer() 85 86 val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB 87 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog) 88 val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog) 89 val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog) 90 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 91 val i_mmio_buffer = LazyModule(new TLBuffer) --- 67 unchanged lines hidden (view full) --- 159 160 beu.module.io.errors <> beu_errors 161 resetDelayN.io.in := reset_vector.fromTile 162 reset_vector.toCore := resetDelayN.io.out 163 hartId.toCore := hartId.fromTile 164 cpu_halt.toTile := cpu_halt.fromCore 165 dontTouch(hartId) 166 dontTouch(cpu_halt) | 83 val xbar_l2_buffer = TLBuffer() 84 85 val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB 86 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog) 87 val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog) 88 val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog) 89 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 90 val i_mmio_buffer = LazyModule(new TLBuffer) --- 67 unchanged lines hidden (view full) --- 158 159 beu.module.io.errors <> beu_errors 160 resetDelayN.io.in := reset_vector.fromTile 161 reset_vector.toCore := resetDelayN.io.out 162 hartId.toCore := hartId.fromTile 163 cpu_halt.toTile := cpu_halt.fromCore 164 dontTouch(hartId) 165 dontTouch(cpu_halt) |
| 166 if (!chi.isEmpty) { dontTouch(chi.get) } |
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| 167 168 if (l2cache.isDefined) { 169 val l2 = l2cache.get.module 170 l2_hint := l2.io.l2_hint 171 l2.io.debugTopDown.robHeadPaddr := DontCare 172 l2.io.hartId := hartId.fromTile 173 l2.io.debugTopDown.robHeadPaddr := debugTopDown.robHeadPaddr 174 l2.io.debugTopDown.robTrueCommit := debugTopDown.robTrueCommit --- 38 unchanged lines hidden --- | 167 168 if (l2cache.isDefined) { 169 val l2 = l2cache.get.module 170 l2_hint := l2.io.l2_hint 171 l2.io.debugTopDown.robHeadPaddr := DontCare 172 l2.io.hartId := hartId.fromTile 173 l2.io.debugTopDown.robHeadPaddr := debugTopDown.robHeadPaddr 174 l2.io.debugTopDown.robTrueCommit := debugTopDown.robTrueCommit --- 38 unchanged lines hidden --- |