xref: /XiangShan/src/main/scala/xiangshan/L2Top.scala (revision 30f35717e23156cb95b30a36db530384545b48a4) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.devices.debug.DebugModuleKey
24import freechips.rocketchip.diplomacy._
25import freechips.rocketchip.interrupts._
26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
27import freechips.rocketchip.tilelink._
28import coupledL2.{EnableCHI, L2ParamKey, PrefetchCtrlFromCore}
29import coupledL2.tl2tl.TL2TLCoupledL2
30import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
31import huancun.BankBitsKey
32import system.HasSoCParameter
33import top.BusPerfMonitor
34import utility._
35import utility.sram.SramBroadcastBundle
36import xiangshan.cache.mmu.TlbRequestIO
37import xiangshan.backend.fu.PMPRespBundle
38import xiangshan.backend.trace.{Itype, TraceCoreInterface}
39
40class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
41  val ecc_error = Valid(UInt(soc.PAddrBits.W))
42}
43
44class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
45  val icache = new L1BusErrorUnitInfo
46  val dcache = new L1BusErrorUnitInfo
47  val l2 = new L1BusErrorUnitInfo
48
49  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
50    List(
51      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
52      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
53      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
54    )
55}
56
57/**
58  *   L2Top contains everything between Core and XSTile-IO
59  */
60class L2TopInlined()(implicit p: Parameters) extends LazyModule
61  with HasXSParameter
62  with HasSoCParameter
63{
64  override def shouldBeInlined: Boolean = true
65
66  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
67    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
68    buffers.zipWithIndex.foreach{ case (b, i) => {
69      b.suggestName(s"${n}_${i}")
70    }}
71    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
72    (buffers, node)
73  }
74  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
75  // =========== Components ============
76  val l1_xbar = TLXbar()
77  val mmio_xbar = TLXbar()
78  val mmio_port = TLIdentityNode() // to L3
79  val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode())
80  val beu = LazyModule(new BusErrorUnit(
81    new XSL1BusErrors(),
82    BusErrorUnitParams(soc.BEURange.base, soc.BEURange.mask.toInt + 1)
83  ))
84
85  val i_mmio_port = TLTempNode()
86  val d_mmio_port = TLTempNode()
87  val icachectrl_port_opt = Option.when(icacheParameters.cacheCtrlAddressOpt.nonEmpty)(TLTempNode())
88  val sep_tl_port_opt = Option.when(SeperateTLBus)(TLTempNode())
89
90  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW
91  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
92  val xbar_l2_buffer = TLBuffer()
93
94  val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB
95  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog)
96  val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog)
97  val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog)
98  val ptw_to_l2_buffer = LazyModule(new TLBuffer)
99  val i_mmio_buffer = LazyModule(new TLBuffer)
100
101  val clint_int_node = IntIdentityNode()
102  val debug_int_node = IntIdentityNode()
103  val plic_int_node = IntIdentityNode()
104  val nmi_int_node = IntIdentityNode()
105  val beu_local_int_source = IntSourceNode(IntSourcePortSimple())
106
107  println(s"enableCHI: ${enableCHI}")
108  val l2cache = if (enableL2) {
109    val config = new Config((_, _, _) => {
110      case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
111        hartId = p(XSCoreParamsKey).HartId,
112        FPGAPlatform = debugOpts.FPGAPlatform,
113        hasMbist = hasMbist
114      )
115      case EnableCHI => p(EnableCHI)
116      case CHIIssue => p(CHIIssue)
117      case BankBitsKey => log2Ceil(coreParams.L2NBanks)
118      case MaxHartIdBits => p(MaxHartIdBits)
119      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
120      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
121    })
122    if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
123    else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
124  } else None
125  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
126
127  // =========== Connection ============
128  // l2 to l2_binder, then to memory_port
129  l2cache match {
130    case Some(l2) =>
131      l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu
132      l2 match {
133        case l2: TL2TLCoupledL2 =>
134          memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get
135        case l2: TL2CHICoupledL2 =>
136          l2.managerNode := TLXbar() :=* l2_binder.get
137          l2.mmioNode := mmio_port
138      }
139    case None =>
140      memory_port.get := l1_xbar
141  }
142
143  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
144  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
145  beu.node := TLBuffer.chainNode(1) := mmio_xbar
146  if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) {
147    icachectrl_port_opt.get := TLBuffer.chainNode(1) := mmio_xbar
148  }
149  if (SeperateTLBus) {
150    sep_tl_port_opt.get := TLBuffer.chainNode(1) := mmio_xbar
151  }
152
153  // filter out in-core addresses before sent to mmio_port
154  // Option[AddressSet] ++ Option[AddressSet] => List[AddressSet]
155  private def cacheAddressSet: Seq[AddressSet] = (icacheParameters.cacheCtrlAddressOpt ++ dcacheParameters.cacheCtrlAddressOpt).toSeq
156  private def mmioFilters = if(SeperateTLBus) (SeperateTLBusRanges ++ cacheAddressSet) else cacheAddressSet
157  mmio_port :=
158    TLFilter(TLFilter.mSubtract(mmioFilters)) :=
159    TLBuffer() :=
160    mmio_xbar
161
162  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
163    val io = IO(new Bundle {
164      val beu_errors = Input(chiselTypeOf(beu.module.io.errors))
165      val reset_vector = new Bundle {
166        val fromTile = Input(UInt(PAddrBits.W))
167        val toCore = Output(UInt(PAddrBits.W))
168      }
169      val hartId = new Bundle() {
170        val fromTile = Input(UInt(64.W))
171        val toCore = Output(UInt(64.W))
172      }
173      val msiInfo = new Bundle() {
174        val fromTile = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
175        val toCore = Output(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
176      }
177      val msiAck = new Bundle {
178        val fromCore = Input(Bool())
179        val toTile = Output(Bool())
180      }
181      val cpu_halt = new Bundle() {
182        val fromCore = Input(Bool())
183        val toTile = Output(Bool())
184      }
185      val cpu_critical_error = new Bundle() {
186        val fromCore = Input(Bool())
187        val toTile = Output(Bool())
188      }
189      val hartIsInReset = new Bundle() {
190        val resetInFrontend = Input(Bool())
191        val toTile = Output(Bool())
192      }
193      val traceCoreInterface = new Bundle{
194        val fromCore = Flipped(new TraceCoreInterface)
195        val toTile   = new TraceCoreInterface
196      }
197      val debugTopDown = new Bundle() {
198        val robTrueCommit = Input(UInt(64.W))
199        val robHeadPaddr = Flipped(Valid(UInt(36.W)))
200        val l2MissMatch = Output(Bool())
201      }
202      val l2Miss = Output(Bool())
203      val l3Miss = new Bundle {
204        val fromTile = Input(Bool())
205        val toCore = Output(Bool())
206      }
207      val clintTime = new Bundle {
208        val fromTile = Input(ValidIO(UInt(64.W)))
209        val toCore = Output(ValidIO(UInt(64.W)))
210      }
211      val chi = if (enableCHI) Some(new PortIO) else None
212      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
213      val pfCtrlFromCore = Input(new PrefetchCtrlFromCore)
214      val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
215      val l2_pmp_resp = Flipped(new PMPRespBundle)
216      val l2_hint = ValidIO(new L2ToL1Hint())
217      val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
218      val l2_flush_en = Option.when(EnablePowerDown) (Input(Bool()))
219      val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool()))
220      val dft = Option.when(hasDFT)(Input(new SramBroadcastBundle))
221      val dft_reset = Option.when(hasMbist)(Input(new DFTResetSignals()))
222      val dft_out = Option.when(hasDFT)(Output(new SramBroadcastBundle))
223      val dft_reset_out = Option.when(hasMbist)(Output(new DFTResetSignals()))
224      // val reset_core = IO(Output(Reset()))
225    })
226    io.dft_out.zip(io.dft).foreach({ case(a, b) => a := b })
227    io.dft_reset_out.zip(io.dft_reset).foreach({ case(a, b) => a := b })
228
229    val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
230
231    val (beu_int_out, _) = beu_local_int_source.out(0)
232    beu_int_out(0) := beu.module.io.interrupt
233
234    beu.module.io.errors.icache := io.beu_errors.icache
235    beu.module.io.errors.dcache := io.beu_errors.dcache
236    resetDelayN.io.in := io.reset_vector.fromTile
237    io.reset_vector.toCore := resetDelayN.io.out
238    io.hartId.toCore := io.hartId.fromTile
239    io.msiInfo.toCore := io.msiInfo.fromTile
240    io.cpu_halt.toTile := io.cpu_halt.fromCore
241    io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore
242    io.msiAck.toTile := io.msiAck.fromCore
243    io.l3Miss.toCore := io.l3Miss.fromTile
244    io.clintTime.toCore := io.clintTime.fromTile
245    // trace interface
246    val traceToTile = io.traceCoreInterface.toTile
247    val traceFromCore = io.traceCoreInterface.fromCore
248    traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder)
249    traceToTile.toEncoder.trap := RegEnable(
250      traceFromCore.toEncoder.trap,
251      traceFromCore.toEncoder.groups(0).valid && Itype.isTrap(traceFromCore.toEncoder.groups(0).bits.itype)
252    )
253    traceToTile.toEncoder.priv := RegEnable(
254      traceFromCore.toEncoder.priv,
255      traceFromCore.toEncoder.groups(0).valid
256    )
257    (0 until TraceGroupNum).foreach{ i =>
258      traceToTile.toEncoder.groups(i).valid := RegNext(traceFromCore.toEncoder.groups(i).valid)
259      traceToTile.toEncoder.groups(i).bits.iretire := RegNext(traceFromCore.toEncoder.groups(i).bits.iretire)
260      traceToTile.toEncoder.groups(i).bits.itype := RegNext(traceFromCore.toEncoder.groups(i).bits.itype)
261      traceToTile.toEncoder.groups(i).bits.ilastsize := RegEnable(
262        traceFromCore.toEncoder.groups(i).bits.ilastsize,
263        traceFromCore.toEncoder.groups(i).valid
264      )
265      traceToTile.toEncoder.groups(i).bits.iaddr := RegEnable(
266        traceFromCore.toEncoder.groups(i).bits.iaddr,
267        traceFromCore.toEncoder.groups(i).valid
268      )
269    }
270
271    dontTouch(io.hartId)
272    dontTouch(io.cpu_halt)
273    dontTouch(io.cpu_critical_error)
274    if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
275
276    val hartIsInReset = RegInit(true.B)
277    hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
278    io.hartIsInReset.toTile := hartIsInReset
279
280    if (l2cache.isDefined) {
281      val l2 = l2cache.get.module
282
283      l2.io.pfCtrlFromCore := io.pfCtrlFromCore
284      l2.io.dft.zip(io.dft).foreach({ case(a, b) => a := b })
285      l2.io.dft_reset.zip(io.dft_reset).foreach({ case(a, b) => a := b })
286      io.l2_hint := l2.io.l2_hint
287      l2.io.debugTopDown.robHeadPaddr := DontCare
288      l2.io.hartId := io.hartId.fromTile
289      l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
290      l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
291      io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
292      io.l2Miss := l2.io.l2Miss
293      io.l2_flush_done.foreach { _ := l2.io.l2FlushDone.getOrElse(false.B) }
294      l2.io.l2Flush.foreach { _ := io.l2_flush_en.getOrElse(false.B) }
295
296      /* l2 tlb */
297      io.l2_tlb_req.req.bits := DontCare
298      io.l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid
299      io.l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready
300      io.l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr
301      io.l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd
302      io.l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size
303      io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill
304      io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate
305      io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill
306      io.perfEvents := l2.io_perf
307
308      val allPerfEvents = l2.getPerfEvents
309      if (printEventCoding) {
310        for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
311          println("L2 Cache perfEvents Set", name, inc, i)
312        }
313      }
314
315      l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid
316      l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready
317      l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head
318      l2.io.l2_tlb_req.resp.bits.pbmt := io.l2_tlb_req.resp.bits.pbmt.head
319      l2.io.l2_tlb_req.resp.bits.miss := io.l2_tlb_req.resp.bits.miss
320      l2.io.l2_tlb_req.resp.bits.excp.head.gpf := io.l2_tlb_req.resp.bits.excp.head.gpf
321      l2.io.l2_tlb_req.resp.bits.excp.head.pf := io.l2_tlb_req.resp.bits.excp.head.pf
322      l2.io.l2_tlb_req.resp.bits.excp.head.af := io.l2_tlb_req.resp.bits.excp.head.af
323      l2.io.l2_tlb_req.pmp_resp.ld := io.l2_pmp_resp.ld
324      l2.io.l2_tlb_req.pmp_resp.st := io.l2_pmp_resp.st
325      l2.io.l2_tlb_req.pmp_resp.instr := io.l2_pmp_resp.instr
326      l2.io.l2_tlb_req.pmp_resp.mmio := io.l2_pmp_resp.mmio
327      l2.io.l2_tlb_req.pmp_resp.atomic := io.l2_pmp_resp.atomic
328      l2cache.get match {
329        case l2cache: TL2CHICoupledL2 =>
330          val l2 = l2cache.module
331          l2.io_nodeID := io.nodeID.get
332          io.chi.get <> l2.io_chi
333          l2.io_cpu_halt.foreach { _:= io.cpu_halt.fromCore }
334        case l2cache: TL2TLCoupledL2 =>
335      }
336
337      beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
338      beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
339    } else {
340      io.l2_hint := 0.U.asTypeOf(io.l2_hint)
341      io.debugTopDown <> DontCare
342      io.l2Miss := false.B
343
344      io.l2_tlb_req.req.valid := false.B
345      io.l2_tlb_req.req.bits := DontCare
346      io.l2_tlb_req.req_kill := DontCare
347      io.l2_tlb_req.resp.ready := true.B
348      io.perfEvents := DontCare
349
350      beu.module.io.errors.l2 := 0.U.asTypeOf(beu.module.io.errors.l2)
351    }
352  }
353
354  lazy val module = new Imp(this)
355}
356
357class L2Top()(implicit p: Parameters) extends LazyModule
358  with HasXSParameter
359  with HasSoCParameter {
360
361  override def shouldBeInlined: Boolean = false
362
363  val inner = LazyModule(new L2TopInlined())
364
365  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
366    val io = IO(inner.module.io.cloneType)
367    val reset_core = IO(Output(Reset()))
368    io <> inner.module.io
369
370    if (debugOpts.ResetGen) {
371      ResetGen(ResetGenNode(Seq(
372        CellNode(reset_core),
373        ModuleNode(inner.module)
374      )), reset, sim = false, io.dft_reset)
375    } else {
376      reset_core := DontCare
377    }
378  }
379
380  lazy val module = new Imp(this)
381}
382