L2Top.scala (42cb64260d34f2b47839d26c7af8b31eef9031c9) L2Top.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.devices.debug.DebugModuleKey
24import freechips.rocketchip.diplomacy._
25import freechips.rocketchip.interrupts._
26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
27import freechips.rocketchip.tilelink._
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.devices.debug.DebugModuleKey
24import freechips.rocketchip.diplomacy._
25import freechips.rocketchip.interrupts._
26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
27import freechips.rocketchip.tilelink._
28import device.MsiInfoBundle
29import coupledL2.{EnableCHI, L2ParamKey, PrefetchCtrlFromCore}
30import coupledL2.tl2tl.TL2TLCoupledL2
31import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
32import huancun.BankBitsKey
33import system.HasSoCParameter
34import top.BusPerfMonitor
35import utility._
36import utility.sram.SramMbistBundle

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167 val fromTile = Input(UInt(PAddrBits.W))
168 val toCore = Output(UInt(PAddrBits.W))
169 }
170 val hartId = new Bundle() {
171 val fromTile = Input(UInt(64.W))
172 val toCore = Output(UInt(64.W))
173 }
174 val msiInfo = new Bundle() {
28import coupledL2.{EnableCHI, L2ParamKey, PrefetchCtrlFromCore}
29import coupledL2.tl2tl.TL2TLCoupledL2
30import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
31import huancun.BankBitsKey
32import system.HasSoCParameter
33import top.BusPerfMonitor
34import utility._
35import utility.sram.SramMbistBundle

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166 val fromTile = Input(UInt(PAddrBits.W))
167 val toCore = Output(UInt(PAddrBits.W))
168 }
169 val hartId = new Bundle() {
170 val fromTile = Input(UInt(64.W))
171 val toCore = Output(UInt(64.W))
172 }
173 val msiInfo = new Bundle() {
175 val fromTile = Input(ValidIO(new MsiInfoBundle))
176 val toCore = Output(ValidIO(new MsiInfoBundle))
174 val fromTile = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
175 val toCore = Output(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
177 }
176 }
177 val msiAck = new Bundle {
178 val fromCore = Input(Bool())
179 val toTile = Output(Bool())
180 }
178 val cpu_halt = new Bundle() {
179 val fromCore = Input(Bool())
180 val toTile = Output(Bool())
181 }
182 val cpu_critical_error = new Bundle() {
183 val fromCore = Input(Bool())
184 val toTile = Output(Bool())
185 }

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238 beu.module.io.errors.icache := io.beu_errors.icache
239 beu.module.io.errors.dcache := io.beu_errors.dcache
240 resetDelayN.io.in := io.reset_vector.fromTile
241 io.reset_vector.toCore := resetDelayN.io.out
242 io.hartId.toCore := io.hartId.fromTile
243 io.msiInfo.toCore := io.msiInfo.fromTile
244 io.cpu_halt.toTile := io.cpu_halt.fromCore
245 io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore
181 val cpu_halt = new Bundle() {
182 val fromCore = Input(Bool())
183 val toTile = Output(Bool())
184 }
185 val cpu_critical_error = new Bundle() {
186 val fromCore = Input(Bool())
187 val toTile = Output(Bool())
188 }

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241 beu.module.io.errors.icache := io.beu_errors.icache
242 beu.module.io.errors.dcache := io.beu_errors.dcache
243 resetDelayN.io.in := io.reset_vector.fromTile
244 io.reset_vector.toCore := resetDelayN.io.out
245 io.hartId.toCore := io.hartId.fromTile
246 io.msiInfo.toCore := io.msiInfo.fromTile
247 io.cpu_halt.toTile := io.cpu_halt.fromCore
248 io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore
249 io.msiAck.toTile := io.msiAck.fromCore
246 io.l3Miss.toCore := io.l3Miss.fromTile
247 io.clintTime.toCore := io.clintTime.fromTile
248 // trace interface
249 val traceToTile = io.traceCoreInterface.toTile
250 val traceFromCore = io.traceCoreInterface.fromCore
251 traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder)
252 traceToTile.toEncoder.trap := RegEnable(
253 traceFromCore.toEncoder.trap,

--- 130 unchanged lines hidden --- 		250 io.l3Miss.toCore := io.l3Miss.fromTile
251 io.clintTime.toCore := io.clintTime.fromTile
252 // trace interface
253 val traceToTile = io.traceCoreInterface.toTile
254 val traceFromCore = io.traceCoreInterface.fromCore
255 traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder)
256 traceToTile.toEncoder.trap := RegEnable(
257 traceFromCore.toEncoder.trap,

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