CSR.scala (68f25d3870164b0cd89ef3e0d089501cb793a703) CSR.scala (05f23f575dc9b9d5ecb9f7884862bbe593024bf4)
1package xiangshan.backend.fu
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import utils._
7import xiangshan._
8import xiangshan.backend._

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355 // slvpredctl: load violation predict settings
356 val slvpredctl = RegInit(UInt(XLEN.W), "h70".U) // default reset period: 2^17
357 csrio.customCtrl.lvpred_disable := slvpredctl(0)
358 csrio.customCtrl.no_spec_load := slvpredctl(1)
359 csrio.customCtrl.waittable_timeout := slvpredctl(8, 4)
360
361 // smblockctl: memory block configurations
362 // bits 0-3: store buffer flush threshold (default: 8 entries)
1package xiangshan.backend.fu
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import utils._
7import xiangshan._
8import xiangshan.backend._

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355 // slvpredctl: load violation predict settings
356 val slvpredctl = RegInit(UInt(XLEN.W), "h70".U) // default reset period: 2^17
357 csrio.customCtrl.lvpred_disable := slvpredctl(0)
358 csrio.customCtrl.no_spec_load := slvpredctl(1)
359 csrio.customCtrl.waittable_timeout := slvpredctl(8, 4)
360
361 // smblockctl: memory block configurations
362 // bits 0-3: store buffer flush threshold (default: 8 entries)
363 val smblockctl = RegInit(UInt(XLEN.W), "h7".U)
363 val smblockctl = RegInit(UInt(XLEN.W), "hf".U & StoreBufferThreshold.U)
364 csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
365
366 val srnctl = RegInit(UInt(XLEN.W), "h1".U)
367 csrio.customCtrl.move_elim_enable := srnctl(0)
368
369 val tlbBundle = Wire(new TlbCsrBundle)
370 tlbBundle.satp := satp.asTypeOf(new SatpStruct)
371 csrio.tlb := tlbBundle

--- 531 unchanged lines hidden --- 		364 csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
365
366 val srnctl = RegInit(UInt(XLEN.W), "h1".U)
367 csrio.customCtrl.move_elim_enable := srnctl(0)
368
369 val tlbBundle = Wire(new TlbCsrBundle)
370 tlbBundle.satp := satp.asTypeOf(new SatpStruct)
371 csrio.tlb := tlbBundle

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