CSR.scala (a13f171cebde32465280fb7792e2ad057dc6425d) CSR.scala (039cdc35f5f3b68b6295ec5ace90f22a77322e02)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24import utility.MaskedRegMap.WritableMask
25import utils._
26import utility._
27import xiangshan.ExceptionNO._
28import xiangshan._
29import xiangshan.backend.fu.util._
30import xiangshan.cache._
31import xiangshan.backend.Bundles.ExceptionInfo
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24import utility.MaskedRegMap.WritableMask
25import utils._
26import utility._
27import xiangshan.ExceptionNO._
28import xiangshan._
29import xiangshan.backend.fu.util._
30import xiangshan.cache._
31import xiangshan.backend.Bundles.ExceptionInfo
32import xiangshan.backend.fu.util.CSR.CSRNamedConstant.ContextStatus
32import xiangshan.backend.fu.NewCSR.CSRNamedConstant.ContextStatus
33import utils.MathUtils.{BigIntGenMask, BigIntNot}
34
35class FpuCsrIO extends Bundle {
36 val fflags = Output(Valid(UInt(5.W)))
37 val isIllegal = Output(Bool())
38 val dirty_fs = Output(Bool())
39 val frm = Input(UInt(3.W))
40}

--- 1650 unchanged lines hidden --- 		33import utils.MathUtils.{BigIntGenMask, BigIntNot}
34
35class FpuCsrIO extends Bundle {
36 val fflags = Output(Valid(UInt(5.W)))
37 val isIllegal = Output(Bool())
38 val dirty_fs = Output(Bool())
39 val frm = Input(UInt(3.W))
40}

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