SC.scala (11269ca741bcbed259cf718605d4720728016f90) SC.scala (8795ffc00d922e6e6cde93b1027e9f79782b0564)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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29
30import chisel3._
31import chisel3.util._
32import org.chipsalliance.cde.config.Parameters
33import scala.{Tuple2 => &}
34import scala.math.min
35import utility._
36import utility.mbist.MbistPipeline
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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29
30import chisel3._
31import chisel3.util._
32import org.chipsalliance.cde.config.Parameters
33import scala.{Tuple2 => &}
34import scala.math.min
35import utility._
36import utility.mbist.MbistPipeline
37import utility.sram.SRAMConflictBehavior
37import utility.sram.SRAMTemplate
38import xiangshan._
39
40trait HasSCParameter extends TageParams {}
41
42class SCReq(implicit p: Parameters) extends TageReq
43
44abstract class SCBundle(implicit p: Parameters) extends TageBundle with HasSCParameter {}

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76 // val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false))
77 val table = Module(new SRAMTemplate(
78 SInt(ctrBits.W),
79 set = nRows,
80 way = 2 * TageBanks,
81 shouldReset = true,
82 holdRead = true,
83 singlePort = false,
38import utility.sram.SRAMTemplate
39import xiangshan._
40
41trait HasSCParameter extends TageParams {}
42
43class SCReq(implicit p: Parameters) extends TageReq
44
45abstract class SCBundle(implicit p: Parameters) extends TageBundle with HasSCParameter {}

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77 // val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false))
78 val table = Module(new SRAMTemplate(
79 SInt(ctrBits.W),
80 set = nRows,
81 way = 2 * TageBanks,
82 shouldReset = true,
83 holdRead = true,
84 singlePort = false,
84 bypassWrite = true,
85 conflictBehavior = SRAMConflictBehavior.BufferWriteLossy,
85 withClockGate = true,
86 hasMbist = hasMbist
87 ))
88 private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeSc", hasMbist)
89 // def getIdx(hist: UInt, pc: UInt) = {
90 // (compute_folded_ghist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits))(log2Ceil(nRows)-1,0)
91 // }
92

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109 val s1_idx = RegEnable(s0_idx, io.req.valid)
110
111 val s1_pc = RegEnable(io.req.bits.pc, io.req.fire)
112 val s1_unhashed_idx = s1_pc >> instOffsetBits
113
114 table.io.r.req.valid := io.req.valid
115 table.io.r.req.bits.setIdx := s0_idx
116
86 withClockGate = true,
87 hasMbist = hasMbist
88 ))
89 private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeSc", hasMbist)
90 // def getIdx(hist: UInt, pc: UInt) = {
91 // (compute_folded_ghist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits))(log2Ceil(nRows)-1,0)
92 // }
93

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110 val s1_idx = RegEnable(s0_idx, io.req.valid)
111
112 val s1_pc = RegEnable(io.req.bits.pc, io.req.fire)
113 val s1_unhashed_idx = s1_pc >> instOffsetBits
114
115 table.io.r.req.valid := io.req.valid
116 table.io.r.req.bits.setIdx := s0_idx
117
118 val per_br_ctrs_unshuffled = table.io.r.resp.data.sliding(2, 2).toSeq.map(VecInit(_))
119 val per_br_ctrs = VecInit((0 until numBr).map(i =>
120 Mux1H(
121 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
122 per_br_ctrs_unshuffled
123 )
124 ))
125
126 io.resp.ctrs := per_br_ctrs
127
117 val update_wdata = Wire(Vec(numBr, SInt(ctrBits.W))) // correspond to physical bridx
118 val update_wdata_packed = VecInit(update_wdata.map(Seq.fill(2)(_)).reduce(_ ++ _))
119 val updateWayMask = Wire(Vec(2 * numBr, Bool())) // correspond to physical bridx
120
121 val update_unhashed_idx = io.update.pc >> instOffsetBits
122 for (pi <- 0 until numBr) {
123 updateWayMask(2 * pi) := Seq.tabulate(numBr)(li =>
124 io.update.mask(li) && get_phy_br_idx(update_unhashed_idx, li) === pi.U && !io.update.tagePreds(li)

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129 }
130
131 val update_folded_hist = WireInit(0.U.asTypeOf(new AllFoldedHistories(foldedGHistInfos)))
132 if (histLen > 0) {
133 update_folded_hist.getHistWithInfo(idxFhInfo).folded_hist := compute_folded_ghist(io.update.ghist, log2Ceil(nRows))
134 }
135 val update_idx = getIdx(io.update.pc, update_folded_hist)
136
128 val update_wdata = Wire(Vec(numBr, SInt(ctrBits.W))) // correspond to physical bridx
129 val update_wdata_packed = VecInit(update_wdata.map(Seq.fill(2)(_)).reduce(_ ++ _))
130 val updateWayMask = Wire(Vec(2 * numBr, Bool())) // correspond to physical bridx
131
132 val update_unhashed_idx = io.update.pc >> instOffsetBits
133 for (pi <- 0 until numBr) {
134 updateWayMask(2 * pi) := Seq.tabulate(numBr)(li =>
135 io.update.mask(li) && get_phy_br_idx(update_unhashed_idx, li) === pi.U && !io.update.tagePreds(li)

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140 }
141
142 val update_folded_hist = WireInit(0.U.asTypeOf(new AllFoldedHistories(foldedGHistInfos)))
143 if (histLen > 0) {
144 update_folded_hist.getHistWithInfo(idxFhInfo).folded_hist := compute_folded_ghist(io.update.ghist, log2Ceil(nRows))
145 }
146 val update_idx = getIdx(io.update.pc, update_folded_hist)
147
137 // SCTable dual port SRAM reads and writes to the same address processing
138 val conflict_buffer_valid = RegInit(false.B)
139 val conflict_buffer_data = RegInit(0.U.asTypeOf(update_wdata_packed))
140 val conflict_buffer_idx = RegInit(0.U.asTypeOf(update_idx))
141 val conflict_buffer_waymask = RegInit(0.U.asTypeOf(updateWayMask))
142
143 val write_conflict = update_idx === s0_idx && io.update.mask.reduce(_ || _) && io.req.valid
144 val can_write = (conflict_buffer_idx =/= s0_idx || !io.req.valid) && conflict_buffer_valid
145
146 when(write_conflict) {
147 conflict_buffer_valid := true.B
148 conflict_buffer_data := update_wdata_packed
149 conflict_buffer_idx := update_idx
150 conflict_buffer_waymask := updateWayMask
151 }
152 when(can_write) {
153 conflict_buffer_valid := false.B
154 }
155
156 // Using buffer data for prediction
157 val use_conflict_data = conflict_buffer_valid && conflict_buffer_idx === s1_idx
158 val conflict_data_bypass = conflict_buffer_data.zip(conflict_buffer_waymask).map { case (data, mask) =>
159 Mux(mask, data, 0.U.asTypeOf(data))
160 }
161 val conflict_prediction_data = conflict_data_bypass.sliding(2, 2).toSeq.map(VecInit(_))
162 val per_br_ctrs_unshuffled = table.io.r.resp.data.sliding(2, 2).toSeq.map(VecInit(_))
163 val per_br_ctrs = VecInit((0 until numBr).map(i =>
164 Mux1H(
165 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
166 per_br_ctrs_unshuffled
167 )
168 ))
169 val conflict_br_ctrs = VecInit((0 until numBr).map(i =>
170 Mux1H(
171 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
172 conflict_prediction_data
173 )
174 ))
175
176 io.resp.ctrs := Mux(use_conflict_data, conflict_br_ctrs, per_br_ctrs)
177
178 table.io.w.apply(
148 table.io.w.apply(
179 valid = (io.update.mask.reduce(_ || _) && !write_conflict) || can_write,
180 data = Mux(can_write, conflict_buffer_data, update_wdata_packed),
181 setIdx = Mux(can_write, conflict_buffer_idx, update_idx),
182 waymask = Mux(can_write, conflict_buffer_waymask.asUInt, updateWayMask.asUInt)
149 valid = io.update.mask.reduce(_ || _),
150 data = update_wdata_packed,
151 setIdx = update_idx,
152 waymask = updateWayMask.asUInt
183 )
184
185 val wrBypassEntries = 16
186
187 // let it corresponds to logical brIdx
188 val wrbypasses = Seq.fill(numBr)(Module(new WrBypass(SInt(ctrBits.W), wrBypassEntries, log2Ceil(nRows), numWays = 2)))
189
190 for (pi <- 0 until numBr) {

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154
155 val wrBypassEntries = 16
156
157 // let it corresponds to logical brIdx
158 val wrbypasses = Seq.fill(numBr)(Module(new WrBypass(SInt(ctrBits.W), wrBypassEntries, log2Ceil(nRows), numWays = 2)))
159
160 for (pi <- 0 until numBr) {

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