refactor(DFT): refactor `DFT` IO (#4530)

feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)

Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Uti

feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)

Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.

After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.

This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.

Thanks, Sam

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chore: fix several deprecation warning (#4352)

feat(dfx): integerate dfx components (#4312)

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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power(bpu): optimize CGE of bpu/predictors_io_update (#3579)

Bpu: Optimize CGE of bpu/predictors_io_update by moving update regs into
predictors, except for the update PC

---------

Co-authore

power(bpu): optimize CGE of bpu/predictors_io_update (#3579)

Bpu: Optimize CGE of bpu/predictors_io_update by moving update regs into
predictors, except for the update PC

---------

Co-authored-by: pengxiao <[email protected]>

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feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\)

feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\) to ensure single-port SRAM access.
* when SRAM is multi-port, the read and write ports of the multi-port
SRAM are gated using different clocks.

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docs: add acknowledgements (#3861)

style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

fix(sc): SCTable dual port SRAM reads and writes to the same address processing (#3671)

bpu: fix SC update sum (#3178)

ftq: cut area of ftq_redirect_mem (#2856)

dlt folded_hist/afhob/lastBrNumOH
ftq_redirect_mem: 247*64->73*64

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: sc

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: scMeta-tageTakens/scUsed/providerResps-unconf/altDiffers/takens;
dlt ITTage: altDiffers/taken
dlt uFTB: pred_way
dlt RAS: sctr/TOSR/NOS

ftq_redirect_sram->ftq_redirect_mem

Co-authored-by: chenguokai <[email protected]>

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BPU: add clock gating (#2733)

Co-authored-by: Liang Sen <[email protected]>

top-down: remove 'sc_disagree' signal from redirect SRAM for FPGAPlatform (#2435)

top-down: move sc from ftb to redirect sram (#2397)

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

bpu: duplicate most possible signal related to npc generation to address (#2254)

high fanout problems

Co-authored-by: Lingrui98 <[email protected]>

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

bpu: add reset back

bpu: refactor prediction i/o bundles