MemBlock.scala (602aa9f1a8fb63310bea30e8b3e247e5aca5f123) MemBlock.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 10 unchanged lines hidden (view full) ---

19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp}
24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
25import freechips.rocketchip.tile.HasFPUParameters
26import freechips.rocketchip.tilelink._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 10 unchanged lines hidden (view full) ---

19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp}
24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
25import freechips.rocketchip.tile.HasFPUParameters
26import freechips.rocketchip.tilelink._
27import device.MsiInfoBundle
28import utils._
29import utility._
30import utility.mbist.{MbistInterface, MbistPipeline}
31import utility.sram.{SramMbistBundle, SramBroadcastBundle, SramHelper}
27import utils._
28import utility._
29import utility.mbist.{MbistInterface, MbistPipeline}
30import utility.sram.{SramMbistBundle, SramBroadcastBundle, SramHelper}
32import system.SoCParamsKey
31import system.{HasSoCParameter, SoCParamsKey}
33import xiangshan._
34import xiangshan.ExceptionNO._
35import xiangshan.frontend.HasInstrMMIOConst
36import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput}
37import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}
38import xiangshan.backend.exu.MemExeUnit
39import xiangshan.backend.fu._
40import xiangshan.backend.fu.FuType._

--- 6 unchanged lines hidden (view full) ---

47import xiangshan.backend.Bundles._
48import xiangshan.mem._
49import xiangshan.mem.mdp._
50import xiangshan.mem.Bundles._
51import xiangshan.mem.prefetch.{BasePrefecher, L1Prefetcher, SMSParams, SMSPrefetcher}
52import xiangshan.cache._
53import xiangshan.cache.mmu._
54import coupledL2.PrefetchRecv
32import xiangshan._
33import xiangshan.ExceptionNO._
34import xiangshan.frontend.HasInstrMMIOConst
35import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput}
36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}
37import xiangshan.backend.exu.MemExeUnit
38import xiangshan.backend.fu._
39import xiangshan.backend.fu.FuType._

--- 6 unchanged lines hidden (view full) ---

46import xiangshan.backend.Bundles._
47import xiangshan.mem._
48import xiangshan.mem.mdp._
49import xiangshan.mem.Bundles._
50import xiangshan.mem.prefetch.{BasePrefecher, L1Prefetcher, SMSParams, SMSPrefetcher}
51import xiangshan.cache._
52import xiangshan.cache.mmu._
53import coupledL2.PrefetchRecv
55import system.HasSoCParameter
54import utility.mbist.{MbistInterface, MbistPipeline}
55import utility.sram.{SramBroadcastBundle, SramHelper}
56
57trait HasMemBlockParameters extends HasXSParameter {
58 // number of memory units
59 val LduCnt = backendParams.LduCnt
60 val StaCnt = backendParams.StaCnt
61 val StdCnt = backendParams.StdCnt
62 val HyuCnt = backendParams.HyuCnt
63 val VlduCnt = backendParams.VlduCnt

--- 225 unchanged lines hidden (view full) ---

289
290 lazy val module = new MemBlockInlinedImp(this)
291}
292
293class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
294 with HasXSParameter
295 with HasFPUParameters
296 with HasPerfEvents
56
57trait HasMemBlockParameters extends HasXSParameter {
58 // number of memory units
59 val LduCnt = backendParams.LduCnt
60 val StaCnt = backendParams.StaCnt
61 val StdCnt = backendParams.StdCnt
62 val HyuCnt = backendParams.HyuCnt
63 val VlduCnt = backendParams.VlduCnt

--- 225 unchanged lines hidden (view full) ---

289
290 lazy val module = new MemBlockInlinedImp(this)
291}
292
293class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
294 with HasXSParameter
295 with HasFPUParameters
296 with HasPerfEvents
297 with HasSoCParameter
297 with HasL1PrefetchSourceParameter
298 with HasCircularQueuePtrHelper
299 with HasMemBlockParameters
300 with HasTlbConst
301 with SdtrigExt
302{
303 val io = IO(new Bundle {
304 val hartId = Input(UInt(hartIdLen.W))

--- 22 unchanged lines hidden (view full) ---

327 val debugTopDown = new Bundle {
328 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W)))
329 val toCore = new MemCoreTopDownIO
330 }
331 val debugRolling = Flipped(new RobDebugRollingIO)
332
333 // All the signals from/to frontend/backend to/from bus will go through MemBlock
334 val fromTopToBackend = Input(new Bundle {
298 with HasL1PrefetchSourceParameter
299 with HasCircularQueuePtrHelper
300 with HasMemBlockParameters
301 with HasTlbConst
302 with SdtrigExt
303{
304 val io = IO(new Bundle {
305 val hartId = Input(UInt(hartIdLen.W))

--- 22 unchanged lines hidden (view full) ---

328 val debugTopDown = new Bundle {
329 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W)))
330 val toCore = new MemCoreTopDownIO
331 }
332 val debugRolling = Flipped(new RobDebugRollingIO)
333
334 // All the signals from/to frontend/backend to/from bus will go through MemBlock
335 val fromTopToBackend = Input(new Bundle {
335 val msiInfo = ValidIO(new MsiInfoBundle)
336 val msiInfo = ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W))
336 val clintTime = ValidIO(UInt(64.W))
337 })
338 val inner_hartId = Output(UInt(hartIdLen.W))
339 val inner_reset_vector = Output(UInt(PAddrBits.W))
340 val outer_reset_vector = Input(UInt(PAddrBits.W))
341 val outer_cpu_halt = Output(Bool())
342 val outer_l2_flush_en = Output(Bool())
343 val outer_power_down_en = Output(Bool())
344 val outer_cpu_critical_error = Output(Bool())
337 val clintTime = ValidIO(UInt(64.W))
338 })
339 val inner_hartId = Output(UInt(hartIdLen.W))
340 val inner_reset_vector = Output(UInt(PAddrBits.W))
341 val outer_reset_vector = Input(UInt(PAddrBits.W))
342 val outer_cpu_halt = Output(Bool())
343 val outer_l2_flush_en = Output(Bool())
344 val outer_power_down_en = Output(Bool())
345 val outer_cpu_critical_error = Output(Bool())
346 val outer_msi_ack = Output(Bool())
345 val inner_beu_errors_icache = Input(new L1BusErrorUnitInfo)
346 val outer_beu_errors_icache = Output(new L1BusErrorUnitInfo)
347 val inner_hc_perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
348 val outer_hc_perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
349
350 // reset signals of frontend & backend are generated in memblock
351 val reset_backend = Output(Reset())
352 // Reset singal from frontend.

--- 1618 unchanged lines hidden (view full) ---

1971 io.memInfo.dcacheMSHRFull := RegNext(dcache.io.mshrFull)
1972
1973 io.inner_hartId := io.hartId
1974 io.inner_reset_vector := RegNext(io.outer_reset_vector)
1975 io.outer_cpu_halt := io.ooo_to_mem.backendToTopBypass.cpuHalted
1976 io.outer_l2_flush_en := io.ooo_to_mem.csrCtrl.flush_l2_enable
1977 io.outer_power_down_en := io.ooo_to_mem.csrCtrl.power_down_enable
1978 io.outer_cpu_critical_error := io.ooo_to_mem.backendToTopBypass.cpuCriticalError
347 val inner_beu_errors_icache = Input(new L1BusErrorUnitInfo)
348 val outer_beu_errors_icache = Output(new L1BusErrorUnitInfo)
349 val inner_hc_perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
350 val outer_hc_perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
351
352 // reset signals of frontend & backend are generated in memblock
353 val reset_backend = Output(Reset())
354 // Reset singal from frontend.

--- 1618 unchanged lines hidden (view full) ---

1973 io.memInfo.dcacheMSHRFull := RegNext(dcache.io.mshrFull)
1974
1975 io.inner_hartId := io.hartId
1976 io.inner_reset_vector := RegNext(io.outer_reset_vector)
1977 io.outer_cpu_halt := io.ooo_to_mem.backendToTopBypass.cpuHalted
1978 io.outer_l2_flush_en := io.ooo_to_mem.csrCtrl.flush_l2_enable
1979 io.outer_power_down_en := io.ooo_to_mem.csrCtrl.power_down_enable
1980 io.outer_cpu_critical_error := io.ooo_to_mem.backendToTopBypass.cpuCriticalError
1981 io.outer_msi_ack := io.ooo_to_mem.backendToTopBypass.msiAck
1979 io.outer_beu_errors_icache := RegNext(io.inner_beu_errors_icache)
1980 io.inner_hc_perfEvents <> RegNext(io.outer_hc_perfEvents)
1981
1982 // vector segmentUnit
1983 vSegmentUnit.io.in.bits <> io.ooo_to_mem.issueVldu.head.bits
1984 vSegmentUnit.io.in.valid := isSegment && io.ooo_to_mem.issueVldu.head.valid// is segment instruction
1985 vSegmentUnit.io.dtlb.resp.bits <> dtlb_reqs.take(LduCnt).head.resp.bits
1986 vSegmentUnit.io.dtlb.resp.valid <> dtlb_reqs.take(LduCnt).head.resp.valid

--- 205 unchanged lines hidden --- 		1982 io.outer_beu_errors_icache := RegNext(io.inner_beu_errors_icache)
1983 io.inner_hc_perfEvents <> RegNext(io.outer_hc_perfEvents)
1984
1985 // vector segmentUnit
1986 vSegmentUnit.io.in.bits <> io.ooo_to_mem.issueVldu.head.bits
1987 vSegmentUnit.io.in.valid := isSegment && io.ooo_to_mem.issueVldu.head.valid// is segment instruction
1988 vSegmentUnit.io.dtlb.resp.bits <> dtlb_reqs.take(LduCnt).head.resp.bits
1989 vSegmentUnit.io.dtlb.resp.valid <> dtlb_reqs.take(LduCnt).head.resp.valid

--- 205 unchanged lines hidden ---