fix(Makefile): sync from yaml prefix if provided (#4560)

feat(AIA): integrate ChiselAIA again (#4509)

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secur

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secure), allowing XiangShan core to function as a secure boot processor
in NoC. For systems that already utilize an MCU for secure boot, access
of XiangShan core should theoretically be non-secure. In the latter
cases, `ENABLE_NS=1` option should be added to the `make` compilation
command.

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feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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feat: make `HART_ID_BITS` configurable in Makefile (#4432)

Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

feat(AIA): integrate ChiselAIA (#4378)

build: can manually disable dfx by `DFX=0` (#4353)

feat(dfx): integerate dfx components (#4312)

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

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submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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build(Makefile): support PLDM_ARGS for make verilog

This change support switching TOPMAIN_ARGS from RELEASE_ARGS to
PLDM_ARGS by setting PLDM=1.

For PLDM_ARGS, we make it consistent with DEBUG_ARGS

build(Makefile): support PLDM_ARGS for make verilog

This change support switching TOPMAIN_ARGS from RELEASE_ARGS to
PLDM_ARGS by setting PLDM=1.

For PLDM_ARGS, we make it consistent with DEBUG_ARGS by default.
User can set PLDM_ARGS in command line to extend it.
Examples as follows:
1. By set PLDM_ARGS="--fpga-platform" and PLDM=1, we will disable
XSLog(including PerfCounters) for both verilog and sim-verilog.
2. By set PLDM_ARGS="--diffest-config ESBINP" and PLDM=1, we can
accelerate Difftest in Palladium through some optimization feature.

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feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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build: support L2 and L3 cache size configuration (#4099)

build: pass -Xmx and -Xss for JVM through make arguments (#3975)

build: pass `CIRCTTargetAnnotation` through `CHISEL_TARGET` (#3974)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)

* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and O

feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)

* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and OpenLLC
* Update build dependencies and submodule initialization rules

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fix(combmem): remove x assignment if ren is low (#3667)

build(Makefile): set default CHI issue to E.b (#3649)

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

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Support query publish version from jar and generated device-tree (#3361)

Signed-off-by: Jiuyue Ma <[email protected]>

Makefile, ArgParser: support for specified CHI issue option (#3340)

Use `ISSUE=B` or `ISSUE=E.b` to specify the released issue of CHI.

emu: fix Makefile MFC_ARGS