Add sbt build support (#857)

Import rocketchip into project

fix output npc bug

ibuf/brq: add bpu update info in backend pipeline

bump chisel to 3.3.2

* This will also bump firrtl to 1.3.2. It seems that the performance of
firrtl compile time is greatly improved. On 9700k, it is improved from
218104.5 ms to 135609.5 ms.

Initial Commit of XiangShan CPU

Use fake Icache to fetch 8 instructions per cycle.

update to chisel3.2

top: add libdevice

first commit