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8795ffc0 |
| 10-Apr-2025 |
Sam Castleberry <[email protected]> |
feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
Hello, this change set is to remove the SRAM read-write conflict handling logic in the frontend, after OpenXiangShan/Uti
feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
Hello, this change set is to remove the SRAM read-write conflict handling logic in the frontend, after OpenXiangShan/Utility#110 has been merged, which adds this logic to the SRAMTemplate. See that pull request and also #4242 for more context.
After this change, I see microbench IPC change 1.397 -> 1.413 and coremark IPC change 2.136 -> 2.147. The branch mispredictions also decreased slightly in both.
This probably cannot be merged automatically, since the utility submodule should point to the new revision after merging instead of the revision in my branch.
Thanks, Sam
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8cfc24b2 |
| 07-Apr-2025 |
Tang Haojin <[email protected]> |
feat(AIA): integrate ChiselAIA again (#4509)
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529b1cfd |
| 17-Mar-2025 |
Tang Haojin <[email protected]> |
Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)
This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.
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7fbc1cb4 |
| 08-Mar-2025 |
Tang Haojin <[email protected]> |
feat(AIA): integrate ChiselAIA (#4378)
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0a16c8b1 |
| 03-Mar-2025 |
Qiming Chu <[email protected]> |
deps: add ivy dependency for sourcecode library (#4341)
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5bd65c56 |
| 14-Jan-2025 |
Tang Haojin <[email protected]> |
feat(Config): add yaml parser for complicated parametrization (#4147)
This commit enables complicated parameterization by yaml parsing. We use circe to do this.
In this commit, we implement 6 confi
feat(Config): add yaml parser for complicated parametrization (#4147)
This commit enables complicated parameterization by yaml parsing. We use circe to do this.
In this commit, we implement 6 configurations:
- PmemRanges: physical memory ranges - PMAConfigs - CHIAsyncBridge: set depth to 0 to disable it - L2CacheConfig - L3CacheConfig - DebugModuleBaseAddr
For better human-readability, this commit changes `WithNKBL2/3` to `L2/3CacheConfig`, changing to case classes, and making the first parameter only accept human-readable size configuration like `0.5 MB` or `256kB`.
This commit also changes PMAConfigs and PmemRanges into List of case classes.
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63e777d1 |
| 14-Jan-2025 |
Tang Haojin <[email protected]> |
fix(build): `gitStatus` should use `Task.Input` (#4168)
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831731b1 |
| 07-Jan-2025 |
Tang Haojin <[email protected]> |
build: add `difftest.test` to build target (#4135)
Needed by verification team.
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8c9adf0c |
| 03-Dec-2024 |
Tang Haojin <[email protected]> |
build: pass -Xmx and -Xss for JVM through make arguments (#3975)
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90804084 |
| 27-Nov-2024 |
Haojin Tang <[email protected]> |
build: bump scala to 2.13.15 and chisel to 6.6.0
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f6f8d1f7 |
| 26-Nov-2024 |
Jiuyue Ma <[email protected]> |
build(jar): Package difftest srcs and ready-to-run binaries into JAR
Signed-off-by: Jiuyue Ma <[email protected]>
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1825b5e5 |
| 26-Nov-2024 |
Jiuyue Ma <[email protected]> |
build(jar): Record commit SHA of each submodule in JAR
Signed-off-by: Jiuyue Ma <[email protected]>
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3956160f |
| 26-Nov-2024 |
Tang Haojin <[email protected]> |
build: bump mill to 0.12.3 (#3933)
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844fba5b |
| 04-Nov-2024 |
Xuan Hu <[email protected]> |
build(version): inject git commit SHA to hardware CommitIDModule (#3818)
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cf7d6b7a |
| 25-Oct-2024 |
Muzi <[email protected]> |
style(Frontend): use scalafmt formatting frontend (#3370)
Format frontend according to the scalafmt file drafted in #3061.
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5c060727 |
| 25-Oct-2024 |
sumailyyc <[email protected]> |
feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)
* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and O
feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)
* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and OpenLLC
* Update build dependencies and submodule initialization rules
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26f0fb0d |
| 14-Aug-2024 |
Jiuyue Ma <[email protected]> |
build: Force to use "en" locale when generating version timestamp (#3376)
Signed-off-by: Jiuyue Ma <[email protected]>
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ce34d21e |
| 09-Aug-2024 |
Jiuyue Ma <[email protected]> |
Support query publish version from jar and generated device-tree (#3361)
Signed-off-by: Jiuyue Ma <[email protected]>
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e3da8bad |
| 22-Jul-2024 |
Tang Haojin <[email protected]> |
build: purge chisel 3 and add deprecation check (#3250)
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039cdc35 |
| 08-Mar-2024 |
Xuan Hu <[email protected]> |
NewCSR: modulized implementation
NewCSR: add Hypervisor CSRs
NewCSR: optimize dump fields using chisel3.reflect.DataMirror
NewCSR: add VirtualSupervisor CSRs
NewCSR: refactor VirtualSupervisor an
NewCSR: modulized implementation
NewCSR: add Hypervisor CSRs
NewCSR: optimize dump fields using chisel3.reflect.DataMirror
NewCSR: add VirtualSupervisor CSRs
NewCSR: refactor VirtualSupervisor and Hypervisor CSRs
* Make sure ValidIO etc function return CSREnumType not EnumType * TODO: AIA for vs
NewCSR: add MachineLevel CSRs
NewCSR: fix alias relationship between hip, hvip and vsip
NewCSR: add SupervisorLevel CSRs
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ae0295f4 |
| 16-Jul-2024 |
Tang Haojin <[email protected]> |
chore: bump chisel 6.5.0 (#3210)
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78a8cd25 |
| 30-Jun-2024 |
zhanglinjuan <[email protected]> |
SoC: an initial version of DummyLLC
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195ef4a5 |
| 28-Jun-2024 |
Tang Haojin <[email protected]> |
build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118)
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4c46d755 |
| 05-Jun-2024 |
Easton Man <[email protected]> |
deps: bump chisel 6.4.0 (#3028)
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11480a7d |
| 20-Apr-2024 |
Tang Haojin <[email protected]> |
chore: bump chisel 6.3.0 (#2904)
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