| #
a58e3351 |
| 23-Sep-2021 |
Li Qianruo <[email protected]> |
Integer SRT16 Divider (#1019)
* New SRT4 divider that may improve timing
See "Digital reurrence dividers with reduced logical depth"
* SRT16 Int Divider that is working properly
* Fix bug r
Integer SRT16 Divider (#1019)
* New SRT4 divider that may improve timing
See "Digital reurrence dividers with reduced logical depth"
* SRT16 Int Divider that is working properly
* Fix bug related to div 1
* Timing improved version of SRT16 int divider
* Add copyright and made some minor changes
* Fix bugs related to div 0
* Fix another div 0 bug
* Fix another special case bug
show more ...
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| #
a3e87608 |
| 28-Jul-2021 |
William Wang <[email protected]> |
Update difftest to use NEMU master branch (#902)
misc: implement difftest as a submodule
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| #
f320e0f0 |
| 24-Jul-2021 |
Yinan Xu <[email protected]> |
misc: update PCL information (#899)
XiangShan is jointly released by ICT and PCL.
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| #
c6d43980 |
| 04-Jun-2021 |
Lemover <[email protected]> |
Add MulanPSL-2.0 License (#824)
In this commit, we add License for XiangShan project.
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| #
53c7ab8b |
| 01-Feb-2021 |
William Wang <[email protected]> |
Merge remote-tracking branch 'origin/master' into mem-timing
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| #
3802dba5 |
| 01-Feb-2021 |
William Wang <[email protected]> |
chore: update debug script
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| #
2199a01c |
| 25-Jan-2021 |
Allen <[email protected]> |
Merge branch 'master' of github.com:RISCVERS/XiangShan into L1DCacheReTest
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| #
b086c6da |
| 13-Jan-2021 |
BigWhiteDog <[email protected]> |
fix bug in core Agent
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| #
ab3aa7ee |
| 09-Dec-2020 |
BigWhiteDog <[email protected]> |
fix peek poke ordering
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| #
4b3d9f67 |
| 01-Dec-2020 |
jinyue110 <[email protected]> |
add icache uncache support
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| #
a9ecfa67 |
| 08-Nov-2020 |
jinyue110 <[email protected]> |
Merge branch 'master' into icache-l1plus
fix conflicts in icache.scala and XSCore
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| #
043203e7 |
| 03-Nov-2020 |
jinyue110 <[email protected]> |
icacheMissQueue: fix resp valid when needflush bug
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| #
b6f269e7 |
| 03-Nov-2020 |
jinyue110 <[email protected]> |
icache: pipeline still going after branch flush
still have bugs in cputests
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| #
3136ee6a |
| 02-Nov-2020 |
LinJiawei <[email protected]> |
Merge 'master' into 'xs-fpu'
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| #
598e480f |
| 31-Oct-2020 |
jinyue110 <[email protected]> |
L1plusCache: fix bug that flush didn't change valid_array
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| #
b7959e5f |
| 30-Oct-2020 |
jinyue110 <[email protected]> |
PASS coremark and microbench but loader(fence.i) FAIL
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| #
6f763b2d |
| 30-Oct-2020 |
jinyue110 <[email protected]> |
connect l1pluscache into memory hierarchy
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| #
3d841bdf |
| 29-Oct-2020 |
jinyue110 <[email protected]> |
Merge branch 'master' into icache-missqueue
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| #
5873524f |
| 28-Oct-2020 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/fix-modulename-in-chiseltest' into update-chisel
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| #
903af6a2 |
| 24-Oct-2020 |
LinJiawei <[email protected]> |
PrintModuleName: must run after wiring transform
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| #
84959497 |
| 21-Oct-2020 |
jinyue110 <[email protected]> |
icacheMissQueue: support different client visit
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| #
e1f91fc1 |
| 21-Oct-2020 |
William Wang <[email protected]> |
[WIP] Lsq: fix stq forward & rollback logic
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| #
3c20517c |
| 20-Oct-2020 |
jinyue110 <[email protected]> |
icacheMissQueue: done and PASS coremark and microbench
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| #
118c6c3c |
| 20-Oct-2020 |
jinyue110 <[email protected]> |
icacheMissQueue: fix bug that s_write_back deadlock
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| #
a684b6ff |
| 19-Oct-2020 |
jinyue110 <[email protected]> |
icacheMissQueue: add debug info and fix deadlock bug
|