difftest - OpenGrok history log for /XiangShan/difftest

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
1191982f	24-Apr-2025	Zhaoyang You <[email protected]>	fix(intr,difftest): add interrupt delegate (#4516) /XiangShan/.gitmodules /XiangShan/ChiselAIA /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scalastyle-config.xml /XiangShan/scalastyle-test-config.xml /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
233e461e	15-Apr-2025	Anzo <[email protected]>	submodule(difftest): add ram_size for setting ref (#4564) /XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml /XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml /XiangShan/.github/workflows/perf.yml /XiangShan/ChiselAIA /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/src/main/resources/config/Default.yml /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/YamlParser.scala /XiangShan/src/main/scala/utils/LowPowerState.scala /XiangShan/src/main/scala/utils/PowerSwitchBuffer.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMAEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/mem/Bundles.scala /XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/utility
dd3d70ba	08-Apr-2025	Yanqin Li <[email protected]>	fix(Uncache): uncache mm store needs difftest to update goldenmem (#4470) /XiangShan/.github/CODEOWNERS /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/.github/workflows/perf.yml /XiangShan/.gitmodules /XiangShan/ChiselAIA /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/scripts/perfcct.py /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/config/Default.yml /XiangShan/src/main/scala/device/IMSICAsync.scala /XiangShan/src/main/scala/device/imsic_axi_top.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/YamlParser.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala
6caa8766	03-Apr-2025	Haojin Tang <[email protected]>	submodule(difftest): bump difftest /XiangShan/.github/workflows/perf.yml /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scalastyle-config.xml /XiangShan/scalastyle-test-config.xml /XiangShan/scripts/constantHelper.py /XiangShan/scripts/requirements.txt /XiangShan/scripts/rolling/.gitignore /XiangShan/scripts/rolling/rollingplot.py /XiangShan/scripts/top-down/configs.py /XiangShan/scripts/top-down/draw.py /XiangShan/scripts/top-down/top_down.py /XiangShan/src/main/resources/config/Default.yml /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/MemEncrypt.scala /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/YamlParser.scala /XiangShan/src/main/scala/utils/LowPowerState.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/utility
08373300	07-Mar-2025	Anzo <[email protected]>	feat(Difftest): add multi-core vector load check (#4361) Currently, we implement the multi core vector load check in difftest. We modified difftest and NEMU and added related content in XiangShan. /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/perf.yml /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/top-down/configs.py /XiangShan/src/main/scala/device/MemEncrypt.scala /XiangShan/src/main/scala/device/MemEncryptUtil.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/PMParameters.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PFEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/BitmapCheck.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/Bundles.scala /XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/frontend/FrontTrigger.scala /XiangShan/utility
2fa6e783	17-Feb-2025	Jiuyue Ma <[email protected]>	submodule(difftest): link libdramsim3.a by `-L/-l` instead of absolute path (#4280) Signed-off-by: Jiuyue Ma <[email protected]> /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/mem/Bundles.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
5299b432	13-Feb-2025	Jiuyue Ma <[email protected]>	submodule(difftest): Bump difftest for bugfix in VCS (#4264) /XiangShan/.github/workflows/artifacts.yml /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/Bundles.scala /XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/utility
680e264b	22-Jan-2025	sinceforYy <[email protected]>	submodule(difftest): bump difftest * commit: 16bb4f35a18c0a5b6d84e866f12263262dc2ab5e Including: * fix(wiring): return source only when not using source annotation (#554) * fix(aia): distinguish ex submodule(difftest): bump difftest * commit: 16bb4f35a18c0a5b6d84e866f12263262dc2ab5e Including: * fix(wiring): return source only when not using source annotation (#554) * fix(aia): distinguish external interrupts sources from CLINT or IMSIC (#556) show more ... /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/config/Default.yml /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
1a9a1641	16-Jan-2025	klin02 <[email protected]>	submodule(difftest): fix scripts for NoC-Difftest Interface /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/difftest /XiangShan/src/main/resources/config/Default.yml /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/YamlParser.scala
a0625f50	16-Jan-2025	Kunlin You <[email protected]>	submodule(difftest): DontTouch difftestIOs when generated by Profile (#4188) Currently we use two-step flow to apply Difftest for NoC XS. We will generate Core along with Difftest Profile in first s submodule(difftest): DontTouch difftestIOs when generated by Profile (#4188) Currently we use two-step flow to apply Difftest for NoC XS. We will generate Core along with Difftest Profile in first step, and generate Difftest by profile in second step. This change add dontTouch to DifftestIOs in second step to make interface compatible for both core and Difftest, and avoid unconnected port being optimized by Chisel. show more ... /XiangShan/difftest /XiangShan/ready-to-run
1697a48e	16-Jan-2025	linzhida <[email protected]>	submodule(difftest): bump difftest to support sync AIA /XiangShan/.github/workflows/emu.yml /XiangShan/README.md /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/openLLC /XiangShan/readme.zh-cn.md /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
b7a63495	16-Jan-2025	NewPaulWalker <[email protected]>	feat(custom, csr): add two custom CSRs mcorepwr and mflushpwr to control power (#4164) Co-authored-by: Zhu Yu <[email protected]> /XiangShan/.github/workflows/artifacts.yml /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/config/Default.yml /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/YamlParser.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/PMParameters.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
718a93f5	03-Jan-2025	Haoyuan Feng <[email protected]>	feat(Svnapot): support Svnapot extension (#4107) /XiangShan/.github/CODEOWNERS /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/utility
75ed9f4b	27-Dec-2024	Tang Haojin <[email protected]>	submodule(difftest): set fork-interval default to 10 seconds (#4095) /XiangShan/.github/filters.yaml /XiangShan/.github/workflows/format.yml /XiangShan/.github/workflows/perf.yml /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala /XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/CtrlUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
ccdd6d2c	09-Dec-2024	zhanglinjuan <[email protected]>	submodule(difftest): bump difftest for Zacas support /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
38c29594	26-Nov-2024	zhanglinjuan <[email protected]>	feat(MemBlock): add support for Zacas extension fix(AtomicsUnit, MemBlock): fix loss of multiple stds In the previous design, AtomicsUnit receives stds from StdExeUnit and arbitrate at most one std feat(MemBlock): add support for Zacas extension fix(AtomicsUnit, MemBlock): fix loss of multiple stds In the previous design, AtomicsUnit receives stds from StdExeUnit and arbitrate at most one std uop for one cycle. This works fine on most of the AMOs and LR/SC because they require only one std uop. However AMOCAS requires at least two std uops, which may be issued from two separate issue queues at the same time, leading to the loss of std uops. This commit fixes this by taking all the outputs of the StdExeUnits into account with arbitration logics. fix(AtomicsUnit): DCache req can only be sent at `s_cache_req` fix(AtomicsUnit, difftest): fix difftest io for atomic events fix(MainPipe): fix precedence of `&` and `=/=` operator fix(MainPipe): AMOCAS should not wait for AMOALU fix(MemBlock): remove unnecessary assertion fix(MainPipe): only CAS instruction can assert `s3_cas_fail` fix(AtomicsUnit): fix bug in data select logic submodule(difftest): bump difftest show more ... /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility
f0a1cc73	02-Dec-2024	Anzo <[email protected]>	submodule(difftest): fix RF updates for floating-point (#3967) /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/yunsuan
d7b0ad94	29-Nov-2024	Tang Haojin <[email protected]>	submodule(difftest): bump difftest (#3956) /XiangShan/.github/filters.yaml /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.mill-version /XiangShan/README.md /XiangShan/build.sc /XiangShan/difftest /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/src/main/scala/device/IMSIC.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/SeqUtils.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/README.md /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/README.md /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/yunsuan
531dd127	21-Nov-2024	sinceforYy <[email protected]>	submodule(difftest): bump difftest * difftest commit: 7d3d2fb71f410c320f62643864d8d06732170280 * Including: * fix(aia): add support for aia xtopei csr (#510) /XiangShan/README.md /XiangShan/difftest /XiangShan/images/xs-arch-kunminghu.svg /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/utility
92f36649	19-Nov-2024	Zehao Liu <[email protected]>	fix(critical-error): critical-error pass early then trap (#3885) * critical-error diff REF as xiangshan pass criticial-error too early * bump difftest to make critical_error more prominent /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
1bf9a598	13-Nov-2024	Anzo <[email protected]>	feat(difftest): add 'pc' and 'robidx' for store event (#3862) /XiangShan/.github/workflows/emu.yml /XiangShan/README.md /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/yunsuan
614d2bc6	08-Nov-2024	HeiHuDie <[email protected]>	feat(zvfh,zfh): add F16 support /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/yunsuan
0b09fccb	08-Nov-2024	lewislzh <[email protected]>	submodule(difftest): expand trapcode to 64bit to fix XStrap * All trap codes outside the enumeration range will be converted to `bad_trap` /XiangShan/difftest /XiangShan/rocket-chip /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/yunsuan
fba8858c	07-Nov-2024	Zehao Liu <[email protected]>	fix(dbltrp):critical-error is not treated as diff error (#3835) /XiangShan/build.sc /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
85a8d7ca	01-Nov-2024	Zehao Liu <[email protected]>	feat(dbltrp) : add support for critical error (#3793) /XiangShan/.github/workflows/format.yml /XiangShan/.github/workflows/perf.yml /XiangShan/.scalafmt.conf /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/imsic_axi_top.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/utils/AXI4Lite.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
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