fix(intr,difftest): add interrupt delegate (#4516)

submodule(ready-to-run): Bump nemu ref in ready-to-run

* NEMU commit:27ca6cb5f7d75014ca795908194bfb39711f9dc2
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv

submodule(ready-to-run): Bump nemu ref in ready-to-run

* NEMU commit:27ca6cb5f7d75014ca795908194bfb39711f9dc2
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig
* riscv64-xs-ref_bitmap_defconfig

Including:
* fix(xtopi): fix m/stopi.IRPIO generation conditions
* fix(vstopi): fix vstopi result selection

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submodule(ready-to-run): bump nemu and spike ref in ready-to-run (#4604)

submodule(ready-to-run): bump nemu ref in ready-to-run (#4566)

feat(PMA, CSR): support PMA CSR configurable (#4233)

fix(vstopi): remove SEI from Candidate 4 (#4533)

* if hvictl.VTI = 0:
* the highest-priority pending-and-enabled major interrupt indicated
* by vsip and vsie other than a supervisor external interru

fix(vstopi): remove SEI from Candidate 4 (#4533)

* if hvictl.VTI = 0:
* the highest-priority pending-and-enabled major interrupt indicated
* by vsip and vsie other than a supervisor external interrupt(code 9),
* using the priority numbers assigned by hviprio1 and hviprio2.
*
* A hypervisor can choose to employ registers hviprio1 and hviprio2
* when emulating the (virtual) supervisor-level iprio array accessed
* indirectly through siselect and sireg (really vsiselect and vsireg)
* for a virtual hart. For interrupts not in the subset supported by
* hviprio1 and hviprio2, the priority number bytes in the emulated
* iprio array can be read-only zeros.

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submodule(ready-to-run): bump nemu ref in ready-to-run (#4523)

submodule(ready-to-run): bump nemu ref in ready-to-run (#4478)

submodule(ready-to-run): Bump nemu ref in ready-to-run (#4416)

Bump nemu ref in ready-to-run

* NEMU commit:c1ae161da33c3b32ef6b79814b48df4adef68b5c
* NEMU configs:
* riscv64-xs-ref_defconfi

submodule(ready-to-run): Bump nemu ref in ready-to-run (#4416)

Bump nemu ref in ready-to-run

* NEMU commit:c1ae161da33c3b32ef6b79814b48df4adef68b5c
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig
* riscv64-xs-ref_bitmap_defconfig

Including:
* config: disable REPORT_ILLEGAL_INSTR by default
* style: style modify on RVV instruction define
* fix(amo): add mmio check for amo/lr/sc instr

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feat(Difftest): add multi-core vector load check (#4361)

Currently, we implement the multi core vector load check in difftest.
We modified difftest and NEMU and added related content in XiangShan.

submodule(ready-to-run): Bump nemu ref in ready-to-run (#4344)

* NEMU commit: b2e8c05ec83f2b2b15b891e361c9a84218436872
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_def

submodule(ready-to-run): Bump nemu ref in ready-to-run (#4344)

* NEMU commit: b2e8c05ec83f2b2b15b891e361c9a84218436872
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig
* Including:
* fix(rvc): NEMU should also properly handle illegal instruction cases in non-dynamic library mode (OpenXiangShan/NEMU#810)
* submodule(ready-to-run): Bump spike ref in ready-to-run
* feat(simpoint): Support writting basic block info (first pc and second pc) into simpoint_bbv file (OpenXiangShan/NEMU#817)
* fix(csr): add prefetch control by spfctl
* fix(csr): remove useless custom csr

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submodule(ready-to-run): Bump spike ref in ready-to-run (#4302)

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:https://github.com/OpenXiangShan/XiangShan/issues/4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>

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submodule(ready-to-run): Bump ready-to-run (#4267)

* NEMU commit: 9d06edda1801e26e2f442e63eb826c2e68478659
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* ri

submodule(ready-to-run): Bump ready-to-run (#4267)

* NEMU commit: 9d06edda1801e26e2f442e63eb826c2e68478659
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig

Including:
* refactor(checkpoint): refactor checkpoint file naming logic
* fix(hgeie): fix macro generation logic for 'HGEIE_MASK'
* feat(checkpoint): support dump flash to file
* fix(priv,exception): Raise exception for unsupported priv-op if
REPORT_ILLEGAL_INSTR was disabled
* config(xs-diff-spike): Disable REPORT_ILLEGAL_INSTR when runing
spike-diff
* fix(scountovf): fix reading scountovf & remove writing scountovf

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submodule(ready-to-run): Bump ready-to-run

* NEMU commit: 38697535806c21e3be5cf86a8c37062362fbaf1e
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs

submodule(ready-to-run): Bump ready-to-run

* NEMU commit: 38697535806c21e3be5cf86a8c37062362fbaf1e
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig

Including:
* fix(aia): external interrupt priority from CLINT or IMSIC

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feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1

Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.

Also, like WFI, interrupts cannot take on wrs instructions.

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submodule(ready-to-run): Bump nemu ref in ready-to-run

* NEMU commit:68c3db24b9a997e847e65893089a608e286c74e3
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
*

submodule(ready-to-run): Bump nemu ref in ready-to-run

* NEMU commit:68c3db24b9a997e847e65893089a608e286c74e3
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig

Including:
* opt(mmu): add an early out fast path (#748)
* refactor(makefile): cleanup (#750)
* fix(help): fix the help of flash-image parameter (#764)
* fix(zvfh): fix zvfh corner case which should support vsew8 (#763)
* fix: allow flash use 512M space (#761)
* fix: replace local riscv64-nutshell-spike-so with ready-to-run (#760)
* feat(difftest): support using difftest override ref flash (#758)
* refactor(Makefile): Migrate other repos build logic to separate makefiles (#766)
* try-fix(difftest attach): Add 'pmp' and 'pmp_cpy' API to difftest_attach, but functionality remains incomplete (#757)
* fix(vaddr): vaddr_read_safe should not check hlvx instruction (#769)
* fix: fix init_difftest wrong definition (#772)
* fix: split LibcheckpointAlpha build process from menuconfig (#771)
* fix(csr, exception): check exception for indirect csr finally
* feat(custom): add two M level custom CSR, mcorepwr and mflushpwr
* feat(difftest): sync custom CSR mflushpwr.l2flushed by difftest
* fix(vslide): fix the decoding of the vslide instruction.
* feat(debug): make log output simpler
* feat(log): improve inst trace log format
* feat: add --store-cpt-in-flash option (#778)
* refactor: wrap function definition with #ifdef (#779)
* feat: replace fixed get_pmem with serialize_base_addr for checkpoint storage (#780)
* feat: support --store-cpt-in-flash option to set serialize_reg_base_addr to flash address (#782)
* fix(aia, exception): Add the missing AIA-related permission checks. (#776)
* configs(gem5-ref): update gem5 ref config (#784)

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submodule(ready-to-run): Bump nemu ref in ready to run
* NEMU commit:2df9c4490fb9cd1759ade099063bd7a6553e306e
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
*

submodule(ready-to-run): Bump nemu ref in ready to run
* NEMU commit:2df9c4490fb9cd1759ade099063bd7a6553e306e
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig

Including:
* fix(zvfh): fix zvfh corner case which should support vsew8 (#763)
* fix(help): fix the help of flash-image parameter (#764)
* refactor(makefile): cleanup (#750)
* opt(mmu): add an early out fast path (#748)
* submodule(ready-to-run): Bump spike ref in ready-to-run
* fix(args): delete restore arg, NEMU could load checkpoint image directly, we donot need this arg now (#753)
* feat(flash): support load flash from cmd line, simply wrapper memory data initialize using fill_memory (#755)
* fix(flash): reprocess 'CONFIG_FLASH_IMG_PATH' with realpath (#756)
* fix(ip,ie): remove some redundant logic related to reading IP and IE.
* fix(hideleg): fix the read value of the LCOFI bit of hideleg.
* fix(intr): fix the interrupt priority of SGEI

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submodule(ready-to-run): Bump spike and nemu ref in ready-to-run

* spike commit: 67ad0cce87b807ac4739c60d186e122bf44f4fcd
* spike config: CPU=XIANGSHAN, CPU=NUTSHELL
* ubuntu 20.04 clang

Including:

submodule(ready-to-run): Bump spike and nemu ref in ready-to-run

* spike commit: 67ad0cce87b807ac4739c60d186e122bf44f4fcd
* spike config: CPU=XIANGSHAN, CPU=NUTSHELL
* ubuntu 20.04 clang

Including:
* difftest: restore difftest_load_flash and add v2
* fix(mmu): replace unknown whitespace characters
* fix(difftrace): use [[unlikely]] from C++20
* feat(ci): add more tests for OSes and compilers
* fix(difftest): include difftest-def.h in spike
* feat(Svnapot): support Svnapot extension
* fix(intr): REF can only check for interrupts when notified by DUT
* fix(raise_intr): fix raise_intr to allow clearing values in mip.
* fix(intr): fix the interrupt priority of LCOFI
* fix(hvip): Fix WMASK of LCOFI bit(bit 13) in hvip

* NEMU commit:0ae504faeccf00edba54478261d8d7571239e599
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig

Including:
* opt(mmu): add some likelyhood mark
* fix(intr): fix the interrupt priority of SGEI
* fix(hideleg): fix the read value of the LCOFI bit of hideleg.
* fix(ip,ie): remove some redundant logic related to reading IP and IE.
* fix(flash): reprocess 'CONFIG_FLASH_IMG_PATH' with realpath
* feat(flash): support load flash from cmd line, simply wrapper memory data initialize using fill_memory
* fix(args): delete restore arg, NEMU could load checkpoint image directly, we donot need this arg now
* submodule(ready-to-run): Bump spike ref in ready-to-run

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feat(Svnapot): support Svnapot extension (#4107)

submodule(ready-to-run): Bump nemu ref in ready-to-run

submodule(ready-to-run): bump nemu ref in ready-to-run

submodule(ready-to-run): bump nemu and spike ref in ready-to-run (#4012)

Bump nemu and spike ref in ready-to-run
* NEMU commit: 4ecc99ec95eb3d72bae79b70d80b0df16c0e3b2f
* NEMU configs:
* risc

submodule(ready-to-run): bump nemu and spike ref in ready-to-run (#4012)

Bump nemu and spike ref in ready-to-run
* NEMU commit: 4ecc99ec95eb3d72bae79b70d80b0df16c0e3b2f
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(store_event): Undefined Behavior that shift
* fix(store_event): differences in display mask
* feat: improve the display of registers

---

* spike commit: 6888be99fd544c5450fbb4fcae35b030d98fbcee
* spike config: CPU=XIANGSHAN

Including:
* feat(Zicclsm): add misalign store check for CPU=XIANGSHAN

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submodule(ready-to-run): bump spike and nemu ref in ready-to-run

* spike commit: 9ab4cebc0caf121695b77f78ca6d2481fe9b182f
* spike config: CPU=XIANGSHAN

Including:
* feat(Zacas): enable Zacas en

submodule(ready-to-run): bump spike and nemu ref in ready-to-run

* spike commit: 9ab4cebc0caf121695b77f78ca6d2481fe9b182f
* spike config: CPU=XIANGSHAN

Including:
* feat(Zacas): enable Zacas entension.

* NEMU commit: bf877e0b34092517c909afc9c58ebc803dd8cf3f
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* config(Zacas): enable Zacas entension.
* submodule(ready-to-run): Bump spike ref in ready-to-run
* ci: add ci tests for Zacas extension.

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submodule(ready-to-run): bump spike ref in ready-to-run (#3995)