ci: use fst instead of vcd (#4503)

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1

Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.

Also, like WFI, interrupts cannot take on wrs instructions.

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ci(perf): add vector hmmer performance test (#4177)

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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ci: archive and update issue B CHI verilog with difftest and test-jar (#4159)

feat(Svnapot): support Svnapot extension (#4107)

submodule(difftest): set fork-interval default to 10 seconds (#4095)

ci: add ci tests for Svpbmt (#4016)

ci: add ci tests for Zacas extension.

fix(Smstateen): fix access check when Smstateen extension enable. (#3978)

* fix the access check for custom CSR and remove the illegal instruction
check when accessing S-mode custom CSR from VS mod

fix(Smstateen): fix access check when Smstateen extension enable. (#3978)

* fix the access check for custom CSR and remove the illegal instruction
check when accessing S-mode custom CSR from VS mode. This is because we
can now use the Smstateen extension to control access to custom content
at different privilege levels.

* fix the misjudgment of the U-mode custom CSR.

* fix the missing access check for the stopi CSR in AIA.

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

ci(nightly): add more ckpts and refactor gcpt loading method

ci(nightly): change checkpoint directory

ci(Zcb): add zcb extension test (#3853)

ci(zvfh,zfh): add f16_test

ci(enable-fork): set fork interval to 10 seconds (#3694)

This change can help us to capture the waveform of problem caused by
hardware stuck. Besides, since we enlarged mmap memory, it may take muc

ci(enable-fork): set fork interval to 10 seconds (#3694)

This change can help us to capture the waveform of problem caused by
hardware stuck. Besides, since we enlarged mmap memory, it may take much
more time on `fork()` syscall. Enlarging the fork interval here also
results better simulation speed in some circumstances.

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fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege

fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege.EX_BP writable in SMP Linux jobs.

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ci(vcs): use coremark-1-iteration instead of microbench (#3605)

ci: randomly delay a few seconds between two `get_free_cores` (#3591)

To reduce the possibility of conflicts.

ci: update nexus-am base ci workload bins (#3491)

The previous riscv64-xs config for nexus-am includes VGA and AUDIO
devices, which do not exist in XiangShan simulation environment. This
patch mod

ci: update nexus-am base ci workload bins (#3491)

The previous riscv64-xs config for nexus-am includes VGA and AUDIO
devices, which do not exist in XiangShan simulation environment. This
patch modifies the workloads used by xiangshan.py to solve the above
problem.

Signed-off-by: "Xu, Zefan" <[email protected]>

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ci: use `num_logical_core` to get numa node (#3489)

script: fix xiangshan.py `with_chiseldb` permanently disabled (#3411)

previous line
```scala
self.with_chiseldb = 0 if args.no_db else None
```
will cause with_chiseldb permanently disabled

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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ci: enable riscv-hyp-tests (#3369)

Because of bugs, riscv-hyp-tests was not added to ci. Now XiangShan
master could pass it, so this patch added it back.

ci: do not consider procname with ssh (#3335)