History log of /XiangShan/src/main/scala/device/AXI4RAM.scala (Results 26 – 38 of 38)
Revision Date Author Comments
# aa38aa4d 11-Sep-2019 William Wang <[email protected]>

fix(cache): fix some problems in 64bit cache, dummy test passed


# ac67b1cb 09-Sep-2019 Zihao Yu <[email protected]>

device: add AXI4Keyboard but not tested, since zedboard does not have PS2 interface


# 9ae8972b 04-Sep-2019 Zihao Yu <[email protected]>

use C array for AXI4RAM in simulation

* now we can pass the image used in AXI4RAM as an argument of emu


# da878e9e 03-Mar-2019 Zihao Yu <[email protected]>

Merge branch 'burst-cache' into gpu


# 3735f2f6 03-Mar-2019 Zihao Yu <[email protected]>

device,AXI4RAM: move assignments of rvalid and bvalid to AXI4Slave


# e68f8385 03-Mar-2019 Zihao Yu <[email protected]>

device,AXI4RAM: support burst write


# 1941909b 02-Mar-2019 Zihao Yu <[email protected]>

device,AXI4RAM: support burst read


# 20592feb 02-Mar-2019 Zihao Yu <[email protected]>

device,AXI4RAM: do not write if the address is out-of-bound


# 8d49e3b9 01-Mar-2019 Zihao Yu <[email protected]>

device,AXI4RAM: fix typo


# 4f6228f7 01-Mar-2019 Zihao Yu <[email protected]>

device: add AXI4Slave to refactor code


# f10a0bcb 01-Mar-2019 Zihao Yu <[email protected]>

device: use BoolStopWatch for axi slave


# 5e80b95b 01-Mar-2019 Zihao Yu <[email protected]>

device,AXI4RAM: refactor index calculation


# ce6a2d5b 01-Mar-2019 Zihao Yu <[email protected]>

bus,axi4,AXI4RAM: move to device package


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