| #
20957846 |
| 10-Jan-2025 |
Zihao Yu <[email protected]> |
fix(device, DebugMoudle): do not use clock with Bool type (#4152)
* gsim can not handle such clocks
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| #
3a520554 |
| 10-Jan-2025 |
Tang Haojin <[email protected]> |
style(DebugModule): remove unnecessary `XSDebugModuleParams` (#4155)
It is more straight-forward to use `DebugModuleParams` in `Config.scala`.
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| #
3a3744e4 |
| 06-Jan-2025 |
chengguanghui <[email protected]> |
feat(DM, hartReset): support `hartReset` which could reset selected harts
* Add hartResetReq in XSNocTop.
* Support `hartReset` features
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| #
f018fe86 |
| 12-Sep-2024 |
chengguanghui <[email protected]> |
fix(DM): remove useless signal `hartResetReq`.
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| #
f7af4c74 |
| 17-Nov-2023 |
chengguanghui <[email protected]> |
Debug Module: cherry-pick debug module from nanhu
|
| #
8891a219 |
| 08-Oct-2023 |
Yinan Xu <[email protected]> |
Bump rocket-chip (#2353)
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| #
935edac4 |
| 21-Sep-2023 |
Tang Haojin <[email protected]> |
chore: remove deprecated brackets, APIs, etc. (#2321)
|
| #
67ba96b4 |
| 02-Jan-2023 |
Yinan Xu <[email protected]> |
Switch to asynchronous reset for all modules (#1867)
This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async
Switch to asynchronous reset for all modules (#1867)
This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.
show more ...
|
| #
361e6d51 |
| 31-May-2022 |
Jiuyang Liu <[email protected]> |
fix for chipsalliance/rocket-chip#2967 (#1562)
* fix for chipsalliance/rocket-chip#2967
* decode: fix width of BitPat(?) in decode logic
Co-authored-by: Yinan Xu <[email protected]>
|
| #
a4e57ea3 |
| 20-Dec-2021 |
Li Qianruo <[email protected]> |
Merge branch 'master' into trigger
|
| #
bc63e578 |
| 08-Dec-2021 |
Li Qianruo <[email protected]> |
Fix various bugs with debug mode and trigger
The bugs are
1. Debug mode ebreak won't cause exception
2. faulty mcontrol load store execute bits
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| #
9aca92b9 |
| 28-Sep-2021 |
Yinan Xu <[email protected]> |
misc: code clean up (#1073)
* rename Roq to Rob
* remove trailing whitespaces
* remove unused parameters
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| #
510ae4ee |
| 03-Sep-2021 |
Jiuyang Liu <[email protected]> |
use ExtModule instead of Chisel3.BlackBox. (#988)
|
| #
c21bff99 |
| 30-Aug-2021 |
Jiawei Lin <[email protected]> |
Bump chisel to 3.5 (#974)
* bump chisel to 3.5
* Remove deprecated 'toBool' && disable tl monitor
* Update RocketChip / Re-enable TLMonitor
* Makefile: remove '--infer-rw'
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| #
d4aca96c |
| 19-Aug-2021 |
lqre <[email protected]> |
core: add basic debug mode features (#918)
Basic features of debug mode are implemented.
* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
core: add basic debug mode features (#918)
Basic features of debug mode are implemented.
* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support
show more ...
|