feat(AIA): integrate ChiselAIA again (#4509)

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secur

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secure), allowing XiangShan core to function as a secure boot processor
in NoC. For systems that already utilize an MCU for secure boot, access
of XiangShan core should theoretically be non-secure. In the latter
cases, `ENABLE_NS=1` option should be added to the `make` compilation
command.

show more ...

feat(backend): make wfi timeout configurable (#4491)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

show more ...

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

show more ...

feat: make `HART_ID_BITS` configurable in Makefile (#4432)

Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

feat(AIA): integrate ChiselAIA (#4378)

build: can manually disable dfx by `DFX=0` (#4353)

feat(dfx): integerate dfx components (#4312)

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

show more ...

submodule(utility): introduce XSPerfLevel for performance counter (#4238)

This change introduce XSPerfLevel, including
`VERBOSE`/`NORMAL`/`CRITICAL`. Only counters with level greater or equal
than t

submodule(utility): introduce XSPerfLevel for performance counter (#4238)

This change introduce XSPerfLevel, including
`VERBOSE`/`NORMAL`/`CRITICAL`. Only counters with level greater or equal
than threhold will be instantiated, which will reduce utilization and
compile time on Pallaium.

PerfLevel therhold can be set in command line, `VERBOSE` by default to
apply all counters.
An example usage as follows:
SIM_ARGS="--perf-level CRITICAL" or
PLDM_ARGS="--perf-level CRITICAL" PLDM=1

PerfLevel param is also `VERBOSE` by default, which means all counters
will be ignored now if threhold greater than that. User can explicitly
set params to keep some important counters instantiated, as follows:
XSPerfAccumulate(xx, yy, perfLevel = XSPerfLevel.CRITICAL)

show more ...

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

show more ...

build: support L2 and L3 cache size configuration (#4099)

Support query publish version from jar and generated device-tree (#3361)

Signed-off-by: Jiuyue Ma <[email protected]>

Makefile, ArgParser: support for specified CHI issue option (#3340)

Use `ISSUE=B` or `ISSUE=E.b` to specify the released issue of CHI.

build: purge chisel 3 and add deprecation check (#3250)

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

show more ...

top: implement XSNoCTop and standalone devices (#3136)

args: modify the optional configuration of the run command (#2984)

Configure restgen as an optional option. RESETGEN is disabled by default
on palladium. It should be noted that multi-core XIANGSHA

args: modify the optional configuration of the run command (#2984)

Configure restgen as an optional option. RESETGEN is disabled by default
on palladium. It should be noted that multi-core XIANGSHAN cannot be
started after enabling RESETGEN, which may still be bug.

show more ...

Config: set minimal hartid width to 6 (#2966)

This can help users who only build one core but then manually
instantiate more than two cores in the SoC.

---------

Signed-off-by: Yangyu Chen <c

Config: set minimal hartid width to 6 (#2966)

This can help users who only build one core but then manually
instantiate more than two cores in the SoC.

---------

Signed-off-by: Yangyu Chen <[email protected]>
Co-authored-by: Yangyu Chen <[email protected]>

show more ...

ArgParser: update MaxHartIdBits for debug module (#2923)

args: add support for disabling AlwaysBasicDB (#2897)

When make, use DISABLE_ALWAYSDB=1 to disable AlwaysBasicDB.

Merge remote-tracking branch 'upstream/master' into tmp-master

Bump difftest and NEMU so (#2782)

* Bump difftest, NEMU so

Difftest:
+ Support ArgParser, use SIM_ARGS="--difftest-config \<CONFIG\>" with
mill command.
+ Support flash without workload for

Bump difftest and NEMU so (#2782)

* Bump difftest, NEMU so

Difftest:
+ Support ArgParser, use SIM_ARGS="--difftest-config \<CONFIG\>" with
mill command.
+ Support flash without workload for VCS/Palladium.
+ Support SquashReplay, which need NEMU store-log feature.
+ Support DRAMSIM3 for VCS/Palladium.
+ Support built-in Perf in DiffTest.
+ Fix typo for privileged

NEMU:
+ Support store-log for new Difftest
+ Align SV39 to XS
+ Compiled on glibc 2.17, compatible for both VCS/Palladium/Verilator.

* Fix typo for privileged

---------

Co-authored-by: Yinan Xu <[email protected]>

show more ...