build: add configuration for `CHIAddrWidth` and `enableL2Flush` (#4621)

feat: add more configuration (#4532)

feat(AIA): integrate ChiselAIA again (#4509)

feat(backend): make wfi timeout configurable (#4491)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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build(config): only allow to turn on or off CHIAsyncBridge (#4187)

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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