History log of /XiangShan/src/main/scala/utils/ArbiterHelper.scala (Results 1 – 3 of 3)
Revision Date Author Comments
# 8891a219 08-Oct-2023 Yinan Xu <[email protected]>

Bump rocket-chip (#2353)


# 935edac4 21-Sep-2023 Tang Haojin <[email protected]>

chore: remove deprecated brackets, APIs, etc. (#2321)


# 6008d57d 16-Mar-2023 happy-lx <[email protected]>

dcache: optimize the ready signal of missqueue (#1965)

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue

dcache: optimize the ready signal of missqueue (#1965)

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue but ready for all same cache block address requests.

This will reduce the number of replays of the load instruction which cannot
enter the missqueue

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