History log of /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala (Results 101 – 125 of 328)
Revision Date Author Comments
# 6810d1e8 25-Oct-2023 sfencevma <[email protected]>

fix params


# b133b458 21-Oct-2023 Xuan Hu <[email protected]>

backend,mem: support HybridUnit


# 59bf8b89 06-Nov-2023 sfencevma <[email protected]>

remove rawNuke (#2460)

Co-authored-by: Lyn <[email protected]>


# 3343d4a5 03-Nov-2023 sfencevma <[email protected]>

LDU: fix rar flush logic (#2445)

* fix rar flush logic

* fix re-fetch and flushPipe logic

* fix rar rollback logic, cancel isFlushPipe

* fix syntax error

* fix selectOldest logic

* fi

LDU: fix rar flush logic (#2445)

* fix rar flush logic

* fix re-fetch and flushPipe logic

* fix rar rollback logic, cancel isFlushPipe

* fix syntax error

* fix selectOldest logic

* fix redirect pc gen loigc

---------

Co-authored-by: Lyn <[email protected]>

show more ...


# 3d5ff993 25-Oct-2023 Haojin Tang <[email protected]>

CtrlBlock: flush snpt correctly when insts cannot enq rob as rob is full


# 71d80353 23-Oct-2023 Haojin Tang <[email protected]>

snapshot: should flush entry that wrap a whole circle


# c4b56310 20-Oct-2023 Haojin Tang <[email protected]>

snapshot: flush conditionally when redirect comes


# 1ca4a39d 15-Oct-2023 Xuan Hu <[email protected]>

backend: add shouldBeInlined = false


# ff7f931d 13-Oct-2023 Xuan Hu <[email protected]>

fix redirect passed to frontend error


# 6ce10964 12-Oct-2023 Xuan Hu <[email protected]>

fix merge errors


# c7d010e5 12-Oct-2023 Xuan Hu <[email protected]>

Merge upstream/master into new-backend


# 83ba63b3 11-Oct-2023 Xuan Hu <[email protected]>

fix merge error


# 4b0d80d8 11-Oct-2023 Xuan Hu <[email protected]>

Merge upstream/master into tmp-backend-merge-master


# 9342624f 10-Oct-2023 Gao-Zeyu <[email protected]>

ftq: add ftq redirect read ahead (#2329)

* FTQ: ftq_redirect_sram & ftb_entry_mem -> read ahead for redirect
* CtrlBlock: support ftqIdx sending early(predMiss/ldReplay/Exception)

Co-authored-by

ftq: add ftq redirect read ahead (#2329)

* FTQ: ftq_redirect_sram & ftb_entry_mem -> read ahead for redirect
* CtrlBlock: support ftqIdx sending early(predMiss/ldReplay/Exception)

Co-authored-by: Jia-Zhijie <[email protected]>

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# b7d9e8d5 28-Sep-2023 xiaofeibao-xjtu <[email protected]>

backend: parameterized generation debug IO and difftest IO


# 96e858ba 24-Sep-2023 Xuan Hu <[email protected]>

backend: add perfDebugInfo


# d8a24b06 20-Sep-2023 zhanglyGit <[email protected]>

Backend: refactor jump targetMem in CtrlBlock


# 8891a219 08-Oct-2023 Yinan Xu <[email protected]>

Bump rocket-chip (#2353)


# 7cf78eb2 22-Sep-2023 happy-lx <[email protected]>

More rolling (#2319)

* util: more rolling support

* observe more rolling cnt at the same time
* diff 2 or more dbs

* fix comment

* remove boringutil

* fix py

* util: move 2 py file t

More rolling (#2319)

* util: more rolling support

* observe more rolling cnt at the same time
* diff 2 or more dbs

* fix comment

* remove boringutil

* fix py

* util: move 2 py file to rolling dir

show more ...


# 935edac4 21-Sep-2023 Tang Haojin <[email protected]>

chore: remove deprecated brackets, APIs, etc. (#2321)


# 95e60e55 18-Sep-2023 Tang Haojin <[email protected]>

LazyModule: do not inline lazy modules in XS (#2311)


# a63155a6 16-Sep-2023 Xuan Hu <[email protected]>

backend,perf: enhance pmc implementation


# 60ebee38 15-Sep-2023 Tang Haojin <[email protected]>

top-down: do not use boring utils (#2304)


# 2326221c 11-Sep-2023 Xuan Hu <[email protected]>

backend: fix rebase bugs


# 17b21f45 11-Sep-2023 Haojin Tang <[email protected]>

top-down: connect missing wires


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