Bump difftest for Chisel-generated interfaces (#2284)

We also add support for difftest with RISC-V Vector extension and nFused.

L2 TLB check is disabled unexpectedly and will be fixed soon.

vector: fix rename for vector instructions
* add old_pdest connection from vecRat to rename

L1 Prefetch (#2261)

* dcache: optimize the ready signal of missqueue

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one ent

L1 Prefetch (#2261)

* dcache: optimize the ready signal of missqueue

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue but ready for all same cache block address requests.

This will reduce the number of replays of the load instruction which cannot
enter the missqueue

* sta, dcache: add A StorePipe in dcache

When the store command passes through the sta pipeline, access the tag
and meta of dcache to determine whether it hits, if it hits, update the
replacement algorithm, and if miss, send a write intent to missqueue

* sta prefetch: add a queue

Enter this queue when the Store Address pipeline sends a request,
determines that it has a cache miss, and the contention for MSHR fails.

The miss request in this queue will be sent to the Store pipeline later.

* sbuffer, dcache: store prefetch burst

A basic implementation of "Boosting Store Buffer Efficiency with
Store-Prefetch Bursts".

Store prefetch at exe is disabled.
Now, when store goes from sq to sbuffer, it will trigger a store
prefetch; when 48 stores fall into 6 cache lines, trigger a store burst
perfetch, which will bring a whole page back into dcache.

* dcache: restric mshr alloc for prefetch req

* restric the max number of entries which can be used by prefetch
* merge two same cache line address prefetch write req
* dynamically detect memset pattern, all mshr can accept prefetch when
pattern is detected

* spb: constantin support

* dcache: fix missqueue prefetch ready

* make prefetch req goes mshr with bigger id

* Revert "spb: constantin support"

This reverts commit 4ee50b89ba4a62cd28fa22d7fbcb2338ad4b1849.

* spb: fix bug in burst generator

* spb: add load prefetch burst support

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* store prefetch: refactor parameters and fix bug

* change some parameters
* fix store pipe bug
* fix load prefetch burst

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* store prefetch: add stride and l2 prefetch

* add a stride prefetcher
* spb and stride will issue prefetch to l2
* when store commits, issue a prefetch to l1

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* spf: change store prefetch structure

* prefetch @ exe -> l2 cache
* stride -> l2 cache

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* Revert "sbuffer: fix replaceIdx"

This reverts commit 40c16aca956af9fb32554a0f12d18db41c22eecd.

* spf: find best interval in stamissqueue

* Revert "spf: find best interval in stamissqueue"

This reverts commit d179f0ce15a5ab989a822de7fe48cc5e2cd96914.

* sms: port store to sms

Miss store will train sms like load.

Now, sms will recieve 4 train sources, 2 for miss load, 2 for miss
store, but prefetcher consume 1 train req per cycle, PrefetchTrainFilter
is added to deal with this case.

* bump huancun

* spf: refactor structure

* miss stores will train sms, and send prefetch to l2
* miss stores will send prefetch to l1 on issue or commit
* spb will send prefetch to l1

* memset: fix memset detection

use lqEmpty to check this

* constantin: storepf constantin support

cherry-pick this to use constantin in storepf

* Revert "constantin: storepf constantin support"

This reverts commit 2b97767b9fa757d920cac3d80d4893a1380592c7.

* storepf: add EnableAtCommitMissTrigger

* trigger prefetch at commit only when the store misses with
EnableAtCommitMissTrigger

* bump coupledl2

* prefetch req from L1 to L2 will Acquire T

* fix merge conflict

* storepf: do not read meta&tag when pf is disabled

* storepf: do not read pcMem when sms store is disabled

* fix verilog check

* fix verilog

* missqueue: support merging prefetch

* prefetch req can be merged to pipeline reg
* merging prefetch write will update cmd
* delay sending out acquire when a prefetch write is about to merge

* missqueue: fix bug of merging prefetch write

* delay sending out acquire when a pipeline reg is about to merging a
prefetch write

* temp: disable store pf

* missqueue: disable merging prefetch

* late prefetch will be ignored
* check alias when merging
* enable store pf at issue

* add L1StreamPrefetcher

* fix assert

* let prefetch req prefer loadunit1 more than 0

* stream prefetcher

* disable stream component in SMS, SMS is only trained on real miss
* add a prefetcher monitor to adjust depth & confidence ..
* add L1 L2 stream prefetch

* add gene support

* Revert "add gene support"

This reverts commit 59ae15640ff3d1cc96347f4d3567d48c740a03bb.

* add miss db

* l1pf: add stride & store source info in cache meta

* add a Stride prefetcher and disable Stride component in sms
* prefetch bit in meta is expanded into 3 bits to store source info of
prefetcher

* prefetch: support sending prefetch req to l3

* l1pf: add FDP & refactor

* add basic FDP counters
* change stride from Block addr to Byte addr
* refactor the code

* bump submodules

* disable load related chiseldb to reduce db size

* fix compile

* fix minimalConfig & enable stream

* fix stride pc problem

* fix minimalconfig compile

* bump submodules

* refactor stream stride helper

* fix compile

* bump huancun

* disable db to save size

* fix l2 assert

* bump submodules

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Haojin Tang <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>

show more ...

rob: fix flush of snapshot in ctrlblock

* Although setting snapshots depends on branch or jump insts, all replay insts can get benefits from this mechanism. So we restore from checkpoints at all red

rob: fix flush of snapshot in ctrlblock

* Although setting snapshots depends on branch or jump insts, all replay insts can get benefits from this mechanism. So we restore from checkpoints at all redirect situation.

show more ...

fix errors in merge master into new-backend

merge master into new-backend

Todo: fix error

backend: refactor

* Prepare for merge master

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* sn

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

show more ...

ldu, stu: Refactoring the code for ldu/stu (#2171)

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_

ldu, stu: Refactoring the code for ldu/stu (#2171)

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_cache_rep and s3_feedbacked

* fix fast replay condition

---------

Co-authored-by: Lyn <[email protected]>

show more ...

CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat

CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat after commit;

show more ...

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

show more ...

lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitSt

lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict when compare SSID

* fix store data wakeup logic

Co-authored-by: Lyn <[email protected]>

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lsu: split lq for larger ooo load window (#2077)

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay qu

lsu: split lq for larger ooo load window (#2077)

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay queue
* load rar queue
* load raw queue
* uncache buffer

It will provide larger ooo load window.

NOTE: IPC loss in this commit is caused by MDP problems, for previous MDP
does not fit new LSU architecture.
MDP update is not included in this commit, IPC loss will be fixed by MDP update later.

---------

Co-authored-by: Lyn <[email protected]>

show more ...

Merge remote-tracking branch 'upstream/master' into new-backend

lsdb: add some information of ls instructions by chiselDB (#1900)

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL

lsdb: add some information of ls instructions by chiselDB (#1900)

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.

* ROB: add inst db drop

globalID signal output is still duplicated

* TLB: TLB will carry mem idx when req and resp

* InstDB: update the TLBFirstIssue

* InstDB: the first version is complete

* InstDB: update decode logic

* InstDB: update ctrlBlock writeback

* Merge: fix bug

* merge: fix compile bug

* code rule: rename debug signals and add db's FPGA signal control

* code rule: update db's FPGA signal control

* ldu: fix isFirstIssue flag for ldflow from rs

* ldu: isFirstIssue flag for hw pf is always false

---------

Co-authored-by: good-circle <[email protected]>
Co-authored-by: William Wang <[email protected]>

show more ...

test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argp

test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

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pf: use next loadPc when pointer chasing

SMS: read pc from pcMem

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

Merge pull request #1829 from OpenXiangShan/master-wfi-update

rob: fix the WFI implementation

top-down: introduce top-down counters and scripts (#1803)

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* :art: After git pull

* :sparkles: Add BranchResteer

top-down: introduce top-down counters and scripts (#1803)

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* :art: After git pull

* :sparkles: Add BranchResteers->CtrlBlock

* :sparkles: Cg BranchResteers after pending

* :sparkles: Add robflush_bubble & ldReplay_bubble

* :ambulance: Fix loadReplay->loadReplay.valid

* :art: Dlt printf

* :sparkles: Add stage2_redirect_cycles->CtrlBlock

* :saprkles: CtrlBlock:Add s2Redirect_when_pending

* :sparkles: ID:Add ifu2id_allNO_cycle

* :sparkles: Add ifu2ibuffer_validCnt

* :sparkles: Add ibuffer_IDWidth_hvButNotFull

* :sparkles: Fix ifu2ibuffer_validCnt

* :ambulance: Fix ibuffer_IDWidth_hvButNotFull

* :sparkles: Fix ifu2ibuffer_validCnt->stop

* feat(buggy): parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* fix(SBuffer): fix idx update logic

* fix(Sbuffer): use `&&` to generate flushMask instead of `||`

* fix(atomic): parameterize atomic logic in `MemBlock`

* fix(StoreQueue): update allow enque requirement

* chore: update comments, requirements and assertions

* chore: refactor some Mux to meet original logic

* feat: reduce `LsMaxRsDeq` to 2 and delete it

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* top-down: add l1, l2, l3 and ddr loads bound perf counters

* top-down: dig into l1d loads bound

* top-down: move memory related counters to `Scheduler`

* top-down: add 2 Ldus and 2 Stus

* top-down: v1.0

* huancun: bump HuanCun to a version with top-down

* chore: restore parameters and update `build.sc`

* top-down: use ExcitingUtils instead of BoringUtils

* top-down: add switch of top-down counters

* top-down: add top-down scripts

* difftest: enlarge stuck limit cycles again

Co-authored-by: gaozeyu <[email protected]>

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rob: disable hasWFI with wfi_enable

csr: add customized bits for fusion and wfi

ctrl: fix jalr target read address

ftq, ctrl: fix compiling errors after rebase