| #
dfde261e |
| 28-Feb-2021 |
ljw <[email protected]> |
Ftq: use regfile instead of 4r_sram (#609)
* Ftq: use reg instead 4r_sram
* Ftq: use delayed value form exu output
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| #
6c0bbf39 |
| 28-Feb-2021 |
ljw <[email protected]> |
Ftq: fix typo (#606)
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| #
2b8b2e7a |
| 28-Feb-2021 |
William Wang <[email protected]> |
Add a naive memory violation predictor (#591)
* WaitTable: add waittable framework
* WaitTable: get replay info from RedirectGenerator
* StoreQueue: maintain issuePtr for load rs
* RS: add
Add a naive memory violation predictor (#591)
* WaitTable: add waittable framework
* WaitTable: get replay info from RedirectGenerator
* StoreQueue: maintain issuePtr for load rs
* RS: add loadWait to rs (only for load Unit's rs)
* WaitTable: fix update logic
* StoreQueue: fix issuePtr update logic
* chore: set loadWaitBit in ibuffer
* StoreQueue: fix issuePtrExt update logic
Former logic does not work well with mmio logic
We may also make sure that issuePtrExt is not before cmtPtrExt
* WaitTable: write with priority
* StoreQueue: fix issuePtrExt update logic for mmio
* chore: fix typos
* CSR: add slvpredctrl
* slvpredctrl will control load violation predict micro architecture
* WaitTable: use xor folded pc to index waittable
Co-authored-by: ZhangZifei <[email protected]>
show more ...
|
| #
fc8a3b3f |
| 26-Feb-2021 |
ljw <[email protected]> |
backend: fix bugs related to fp exu write back (#595)
* Backend: fix some bugs related to exu write
* Roq: revert to perv verision
* Fix fp write back bugs
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| #
0d50774a |
| 24-Feb-2021 |
ljw <[email protected]> |
CtrlBlock: add 1 cycle in redirect path (#582)
|
| #
049559e7 |
| 23-Feb-2021 |
Yinan Xu <[email protected]> |
dispatch1: compute lsqNeedAlloc in rename for better timing
|
| #
89c124cd |
| 17-Feb-2021 |
Lingrui98 <[email protected]> |
Merge remote-tracking branch 'origin/master' into dev-sc
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| #
ce14a4f1 |
| 09-Feb-2021 |
wangkaifan <[email protected]> |
Merge branch 'dual-dev' into dual-dev-clean
|
| #
3d499721 |
| 09-Feb-2021 |
wangkaifan <[email protected]> |
difftest: eliminate original difftest framework
|
| #
0e4c26cb |
| 04-Feb-2021 |
zoujr <[email protected]> |
Merge branch 'master' into ftq-loop
|
| #
f6fc1a05 |
| 04-Feb-2021 |
zoujr <[email protected]> |
LoopPredictor: Modify the loop predictor to adapt to ftq
|
| #
3fb288ee |
| 03-Feb-2021 |
Yinan Xu <[email protected]> |
Merge branch 'master' into dual-dev
|
| #
63038220 |
| 02-Feb-2021 |
wangkaifan <[email protected]> |
Merge branch 'master' of https://github.com/RISCVERS/XiangShan into dual-dev
|
| #
eab03f65 |
| 02-Feb-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into opt-exception
|
| #
80317a1a |
| 02-Feb-2021 |
Yinan Xu <[email protected]> |
Merge pull request #534 from RISCVERS/linux-debug
CtrlBlock: fix many 'flush' related bugs
|
| #
27c1214e |
| 01-Feb-2021 |
LinJiawei <[email protected]> |
CtrlBlock: don't send backendRedirect when there is a flush last cycle
linux can run more cycles after this change
|
| #
01f25297 |
| 01-Feb-2021 |
Lingrui98 <[email protected]> |
redirect: fix a bug where redirect generator gives wrong target
|
| #
2681d146 |
| 01-Feb-2021 |
wangkaifan <[email protected]> |
Merge branch 'linux-debug' into dual-dev
|
| #
aa1bcedb |
| 01-Feb-2021 |
wangkaifan <[email protected]> |
Merge branch 'linux-debug' into dual-dev
|
| #
1670d147 |
| 01-Feb-2021 |
Lingrui98 <[email protected]> |
ftq: save two packet pcs for timing considerations
|
| #
7f4d5f59 |
| 01-Feb-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/linux-debug' into opt-exception
|
| #
bbd262ad |
| 01-Feb-2021 |
LinJiawei <[email protected]> |
Backend: delay all flushes for 1 cycle
|
| #
66ed03db |
| 01-Feb-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/linux-debug' into opt-exception
|
| #
cea0b79d |
| 01-Feb-2021 |
LinJiawei <[email protected]> |
Rename: delay 'flush' 1 cycle in CtrlBlock
|
| #
36380705 |
| 01-Feb-2021 |
wangkaifan <[email protected]> |
Merge branch 'master' into dual-dev
|