fix(dcsr): debug support critical error state

* support nmip, cetrig, extcause fileds in dcsr.
* critical error state enter dmode when dcsr.cetrig assert.

feat(difftest): add 'pc' and 'robidx' for store event (#3862)

feat(dbltrp) : add support for critical error (#3793)

fix(vector,exception,ctrlblock): block rob enq when VecExcpMod is busy

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

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fix(vtypegen): fix initial condition after receive redirect (#3664)

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

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fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Backend: support Shvstvala and Sstvala extension

Trigger: refactor trigger information in pipeline. (#3403)

DebugModule: Fix bug of singleStep. (#3395)

* `SingleStepStatus` should not be cleared by redirect before hart enter
debugMode.
* singleStep should block rob compress in `rename`.

Decode and Ibuffer: change decodeCanAccept and bypass logic for fix timing

PcTargetMem: Fixed a bug that caused the backend to be unable to read the newest target (#3269)

Decode: add DecodeBuf for fix timing of ready to Ibuffer (#3293)

Redirect fix timing (#3209)

PerfEvent: refactor perfevents in Backend

* add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler
* add busytable event
* move collecting perfevents from

PerfEvent: refactor perfevents in Backend

* add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler
* add busytable event
* move collecting perfevents from `ctrlBlock` to `backend`
* change `perfEventsCtrl` into `perfEventsBackend`

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NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inva

NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inval`, `sfence.inval.ir`, `hfence.gvma`, `hinval.gvma`, `hfence.vvma` and `hinval.vvma`.

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NewCSR: make XRET use redirect bundle to pass target instead of csr-rob direct connection

* TODO: remove isXRet signal from RobCSRIO.
* Add ftqIdx,ftqOffset in CSR Fu.
* XRet need not flushPipe

Backend,Frontend: pass flag of FtqPtr to TargetMem to avoid read out-of-date predict target (#3184)

* Hold newest predict target everytime it is updated by frontend.
* Don't use out-of-date predict

Backend,Frontend: pass flag of FtqPtr to TargetMem to avoid read out-of-date predict target (#3184)

* Hold newest predict target everytime it is updated by frontend.
* Don't use out-of-date predict value even if FtqIdx match.

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CtrlBlock: writeback to rob remove flush for fix timing (#3181)

vtype: use the vtype stored in rob enq to vtypebuffer's snapshot (#3180)

Rob: fix bug of exception (#3161)

1.when writeback exception, rob may commit next cycle. 2.when fulshOut,
rob commit info to ftq may 4 cycle after redirect but redirect info to
ftq need 5 cycle.

Backend: fix ready timing from dispatch to frontend (#3127)

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions exce

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions except above instructions, raise
illegal instruction exception
* when modify vstart, blockback and flushpipe

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