DecodeStage: block vector inst when vtype is resuming

Int Regfile: Split-bank read

CtrlBlock: fix bug of rob compress wb count

ctrlblock: timing optimize of wb counter to rob

backend: implement uncertain latency exeUnit WbArbiter

Dispatch: split int dispatch to two regions

CtrlBlock: fix snpt bug when robIdx out of index

ctrlblock: optimize writeback nums to rob

jump: separate src and pc

IQ: remove unused pc and ftqptr

Rab: shrink rab entry width

Rob: optimize timing, remove vconfig debugIO

Backend: fix allow enqueue when init

CtrlBlock: add enable to RegNext

stIn: connect missing wire

Merge remote-tracking branch 'upstream/master' into backendq

Backend: add VTypeBuffer to deduce size of rob

backend: remove renameOut pipeline

CtrlBlock optimize timing: read rat at rename stage, piped walkVtype to decode

remove rename and dispatch pipeline

Backend: add en to RegNext

CtrlBlock: add en to RegNext

decode: refactor decode stage

* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in

decode: refactor decode stage

* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in decodeComp, the count of rename ready uops will be send to rename stage.

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Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

* memblock: add a Reg between inner/outer reset_vec

* missqueue: make mem_grant always ready

* Enable ECC path again

* remove fast replay reorder logic

* l1pf: use chosen of arbiter to improve timing

* remove reorder remain logic

* mq: use ParallelORR instead of orR

* Strengthen the conditions for load to load path for timing

* fix load to load data select for timing

* refactoring lq replay valid logic

* fix replay port

* fix load unit s0 arbitor logic

* add topdown wiring

* fix ldu ecc path

* remove lateKill

* ecc: physically remove ecc in DataArray

* loadpipe: use ParallelORR and ParallelMux for timing

* mainpipe: use ParallelMux and ParallelorR for timing

* fix fast replay is killed at s1

* fix replay cancel logic

* fix mq nack feedback logic

* sms: fix pf queue tlb req logic for timing

* kill load at s1

* fix loadqueuereplay enq logic

* opt raw rollback arbiter logic

* fix ecc_delayed writeback logic

* train all l1 pf and sms at load s3 for better timing

* disable load to load forward

* Revert "kill load at s1"

This reverts commit 56d47582ad4dd9c83373fb2db2a0709075485d4d.

* fix s0 kill logic

* ITLBRepeater: Add one more buffer when PTW resp

* remove trigger

* fix feedback_slow logic

* add latch in uncachebuffer rollback

* remove trigger in port

* fast replay: use dcache ready

* fix replay logic at s1

* uncache: fix uncache writeback

* fix delay kill logic

* fix clean exception loigc at s3

* fix ldu rollback logic

* fix ldu rollback valid logic

---------

Co-authored-by: sfencevma <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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hpm: fix selection logic and typo (#1618) (#2483)

Co-authored-by: Chen Xi <[email protected]>