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dd980d61 |
| 20-Nov-2024 |
Xu, Zefan <[email protected]> |
fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)
We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is
fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)
We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is an GPAMem which
storages the whole 64-bit gpaddr, but it does not pass to CSR correctly,
due to incorrect width of trapPCGPA in module NewCSR and bundle
TrapEntryEventInput. This patch fixes this.
---------
Co-authored-by: ngc7331 <[email protected]>
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faf7d50b |
| 26-Oct-2024 |
Xiaokun-Pei <[email protected]> |
fix(PTW, RVH): modify the logic of checking high bits of gpaddr (#3679)
- In PTW, use a reg to store gvpn to check the high bits.
- The len of gvpn(wire type) is wrong. It should be ptePPNLen.
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ad415ae0 |
| 21-Sep-2024 |
Xiaokun-Pei <[email protected]> |
feat(trap): support m/htinst for specific G-stage translation (#3604)
According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t
feat(trap): support m/htinst for specific G-stage translation (#3604)
According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval
"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.
This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.
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9c0fd28f |
| 18-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: fix atp CSRs PPN mask
* The writable length of satp is `PAddrBits - PageOffsetWidth`. * The writable length of vsatp varies with hgatp.MODE. * When hgatp.MODE is `Bare`, it's `PAddrBits -
NewCSR: fix atp CSRs PPN mask
* The writable length of satp is `PAddrBits - PageOffsetWidth`. * The writable length of vsatp varies with hgatp.MODE. * When hgatp.MODE is `Bare`, it's `PAddrBits - PageOffsetWidth`. * When hgatp.MODE is `Sv39x4`, it's `41 - PageOffsetWidth`. * The writable length of hgatp is `PAddrBits - PageOffsetWidth`. Since the root page table is 16 KiB and must be aligned to a 16-KiB boundary, the lowest two bits of the physical page number (PPN) in hgatp always read as zeros. * A write to hgatp with an unsupported MODE value is not ignored as it is for satp. * Instead, the fields of hgatp are WARL in the normal way, when so indicated.
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3adc7007 |
| 21-May-2024 |
Tang Haojin <[email protected]> |
GPAMem: fix gpa offset concatenation (#2991)
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bad60841 |
| 10-May-2024 |
Xiaokun-Pei <[email protected]> |
IFU & GPAMem, RVH: fix the bug about getting gpa (#2960)
1. Delete some useless codes about gpaddr.
2. fix the bugs about wrong gpa was writen in mtval2 or htval when guest
page fault occured
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6f483f86 |
| 13-Apr-2024 |
Xuan Hu <[email protected]> |
Backend: add solution for inst gpaddr
* Use ifu write gpaddr
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