History log of /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala (Results 1 – 11 of 11)
Revision Date Author Comments
# 97929664 23-Aug-2024 Xiaokun-Pei <[email protected]>

MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)


# 3ea4388c 20-Aug-2024 Haoyuan Feng <[email protected]>

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>


# 5f7c1a77 08-Aug-2024 linzhida <[email protected]>

BranchUnit: fix a bug that the pc vaddr only support 39 bits in branch unit.


# fbe46a0a 29-May-2024 xiaofeibao <[email protected]>

DataConfig: remove VfRegSrcDataSet


# 07b5cc60 29-May-2024 xiaofeibao <[email protected]>

Backend: change MaskSrcData VConfigData to V0Data VlData


# 3da89fc0 29-May-2024 xiaofeibao <[email protected]>

Backend: vfexu add V0RD VlRD


# 2aa3a761 27-May-2024 sinsanction <[email protected]>

Backend: add some basic signals for v0 & vl split


# 60f0c5ae 26-Apr-2024 xiaofeibao <[email protected]>

Backend: add FpScheduler


# 5edcc45f 08-Mar-2024 Haojin Tang <[email protected]>

Parameters: remove write port configs for store


# 5d2b9cad 19-Jul-2023 Xuan Hu <[email protected]>

backend: add BypassNetwork


# 730cfbc0 16-Apr-2023 Xuan Hu <[email protected]>

backend: merge v2backend into backend