History log of /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala (Results 1 – 7 of 7)
Revision Date Author Comments
# 2d875144 28-Jun-2024 sinsanction <[email protected]>

DataSource: fix type v0 and add type regcache


# f8e432b7 30-May-2024 xiaofeibao <[email protected]>

DataSource: add readV0 for vec src0/1/2


# 4fa640e4 29-Mar-2024 sinsanction <[email protected]>

IssueQueue, BypassNetwork: add 1 cycle delay when writing back to vf regfile


# 712a039e 18-Jan-2024 xiaofeibao-xjtu <[email protected]>

backend: og1 src select timing optimize


# c4fc226a 16-Jan-2024 xiaofeibao-xjtu <[email protected]>

backend: add DataSource anotherReg


# 0dbae67a 16-Jan-2024 xiaofeibao-xjtu <[email protected]>

DataSource: increase to 5 types


# c0be7f33 19-Jul-2023 Xuan Hu <[email protected]>

backend,iq: split wake up bundles, add cancel bundle

* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
*

backend,iq: split wake up bundles, add cancel bundle

* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
* Add srcTimer in StatusArray to record the cycles src has been waked up
* Add dataSources in StatusArray to record the source of src data (reg, forward, bypass or none)
* Remove useless ready field in StatusArray

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