feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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fix(FusionDecoder): tie output to false when disabled (#4456)

fix(amocas): fix amocas.q to avoid stalls (#4435)

when rd is equal to rs1, uop1 will write rd, while uop2 and uop3 of
amocas.q need rs1 as src, which cause a RAW stalls.

However, rs1, the address o

fix(amocas): fix amocas.q to avoid stalls (#4435)

when rd is equal to rs1, uop1 will write rd, while uop2 and uop3 of
amocas.q need rs1 as src, which cause a RAW stalls.

However, rs1, the address of load and store, is used in uop1, we donot
need rs1 in other uops.

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fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)

Currently, only the CHI version of XS supports the CBO instruction , so
we are adding the illegal instruction to the Tl

fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)

Currently, only the CHI version of XS supports the CBO instruction , so
we are adding the illegal instruction to the TlieLink version of XS.

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fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'de

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'dest after rename,
which cause stalls.

In this commit, we set src2 in uop0 and dest in uop1, avoiding stalls by
renaming.

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feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1

Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.

Also, like WFI, interrupts cannot take on wrs instructions.

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feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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fix(zvfh): fix zvfh corner case which should support vsew8
* vfwcvtfx,vfwcvtfxu,vfncvtxuf,vfncvtxf,vfncvtrodxuf,vfncvtrodxf should support vsew8

fix(FusionDecoder): instructions may be HINT cannot be fused (#4108)

style(decode): add comments and small modification on code style (#3774)

timing(Vector,Decode): judge isComplex by inst encoding directly (#4066)

fix(fpDecoder): fix bug of fmt

fix(decode): scala fp fu's fmt use fpuCtrl instead of vsew

timing(DecodeUnit): remove fpToVecDecoder

timing(decode): dequeue uops by indexing in order in DecodeUnitComp (#4025)

fix(uopsplit): set vector instructions never use simple split type (#4024)

* when use simple split type, instruction cannot send to complex decoder
and not do the exception check
* vs dirty is set

fix(uopsplit): set vector instructions never use simple split type (#4024)

* when use simple split type, instruction cannot send to complex decoder
and not do the exception check
* vs dirty is setted when split type is not simple

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feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(Backend): add support for Zacas extension

misc: remove assert temporarily

area(decode): move vecExceptionGen to complex docoder (#3961)

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different instructions may have same fuoptype, so we need to check
both futype and fuoptype to distinguish the instructions

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fix(aes): fix exception check for aes64ks1i.

rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value` port. The original implementation
caused all perf event information for PTW to be printed as
`perfEventsPTW`, making them indistinguishable.

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fix(vnclip): use uimm instead of imm for vnclip_wi instructions (#3894)

Although the vs2 used by the vnclip instruction is signed, the immediate
number is unsigned.

busytable: support eliminate old vd when read vl's state

fix(FPDecoder):fix fmaTable

fix some bug