fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)

Currently, only the CHI version of XS supports the CBO instruction , so
we are adding the illegal instruction to the Tl

fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)

Currently, only the CHI version of XS supports the CBO instruction , so
we are adding the illegal instruction to the TlieLink version of XS.

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feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1

Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.

Also, like WFI, interrupts cannot take on wrs instructions.

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style(decode): add comments and small modification on code style (#3774)

timing(Vector,Decode): judge isComplex by inst encoding directly (#4066)

timing(DecodeUnit): remove fpToVecDecoder

feat(Backend): add support for Zacas extension

misc: remove assert temporarily

area(decode): move vecExceptionGen to complex docoder (#3961)

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different instructions may have same fuoptype, so we need to check
both futype and fuoptype to distinguish the instructions

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fix(aes): fix exception check for aes64ks1i.

rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.

busytable: support eliminate old vd when read vl's state

feat(zvfh,zfh): add F16 support

fix(zfh): flh/fsh should raise illegal exception when fs is off.

feat(zihintpause): support zihintpause

feat(decode): no rob compress when is last in ftq

set canRobCompress to false when a instruction is the last one in
its Ftq entry.

fix(vector, decode): use OPFV[VF] encoded in inst to check if need FS not Off (#3696)

* When FS is Off, executing vfslide1up/down should raise illegal instruction exception

feat(rv64v): support first only fault instruction

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s,

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s, h}.
* Support xenvcfg.CBIE = Flush(0b01)
* Decode
* Use the illegalInst and virtualInst conditions from CSR to assert
EX_II or EX_VI.
* Convert CBO.INVAL to CBO.FLUSH when envcfg.CBIE === EnvCBIE.Flush.

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fix(Svinval): make all insts in Sinval behavior like fence to avoid software wrong usage (#3534)

* Since software cannot promiss all sinval.vma between sfence.w.inval
and sfence.inval.ir, we make s

fix(Svinval): make all insts in Sinval behavior like fence to avoid software wrong usage (#3534)

* Since software cannot promiss all sinval.vma between sfence.w.inval
and sfence.inval.ir, we make sinval.vma always wait forward.

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Backend: stop block_backward for csrr, in rename stage

accelerate read only csrr by pipelining

fix(rv64v): set vwredsum instructions always depend on oldvd (#3495)

* vwredsum's split type is UopSplitType.VEC_VWW

feat(riscv64): support RISC-V Smrnmi extension (#3480)

feat(riscv64): Support RISC-V Zfa extension

* Support fli.{h.s.d}, fminm.{h.s.d}, fmaxm.{h.s.d}
* Support fround.{h.s.d}, froundnx.{h.s.d}, fcvtmod.w.d
* Support fleq.{h.s.d}, fltq.{h.s.d}

feat(rv64): add Zimop extension support

* All MOP.R.n and MOP.RR.n only update rd with 0s. This would be changed when any MOP redefined by some other extensions.
* Define all MOP.R.n and MOP.RR.n se

feat(rv64): add Zimop extension support

* All MOP.R.n and MOP.RR.n only update rd with 0s. This would be changed when any MOP redefined by some other extensions.
* Define all MOP.R.n and MOP.RR.n seperated instruction name for future easier modification, since any one of MOP could be meaningful instruction in the future.
* If rd is not 0, mop instructions will convert to a move instruction, which move x0 to rd.
* If rd is 0, mop instructions will convert to a addi intruction, whose rs0 is x0 and imm is 0.

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