fix(FusionDecoder): tie output to false when disabled (#4456)

fix(FusionDecoder): instructions may be HINT cannot be fused (#4108)

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
w

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
widths of all read/write ports were set to 6, which works well but is
not parameterized. Now these widths are modified to be controlled by
parameters.

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DecodeUnit: clean up decoder (#2943)

This commit sorts out decode by the ratified name of each extension for
Zb* and Zk*. And add some comments about RV32 concerns we may need
someday.

Signed-o

DecodeUnit: clean up decoder (#2943)

This commit sorts out decode by the ratified name of each extension for
Zb* and Zk*. And add some comments about RV32 concerns we may need
someday.

Signed-off-by: Yangyu Chen <[email protected]>

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Merge remote-tracking branch 'upstream/master' into backendq

FusionDecoder: prevent fusion when inst2 rs1 == rs2 (#2466) (#2513)

FusionDecoder: prevent fusion when inst2 rs1 == rs2 (#2466)

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

Backend, Fusion: another implementation for instruction fusion case 'lui + addi(w)' without widening imm bits

Backend, Fusion: support instruction fusion case 'lui + addiw'

Backend, Fusion: support instruction fusion case 'lui + addi'

mod: refactor the code of encoding

backend: merge v2backend into backend

v2backend: huge tmp commit

Merge remote-tracking branch 'origin/master' into rf-after-issue

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

rename: use intRat for vconfig; add a vec read port

fusion: deassert out.valid for invalid instructions (#1634)

This commit fixes the bug that instructions with exceptions may trigger
instruction fusion if the previous instruction at the same positi

fusion: deassert out.valid for invalid instructions (#1634)

This commit fixes the bug that instructions with exceptions may trigger
instruction fusion if the previous instruction at the same position is
fused. When the input instruction pair is invalid, the fusion decoder
should always set out.valid to false.B at the next cycle.

The bug is caused by the RegEnable for instrPairValid, which should be
updated at every clock cycle.

Should fix the error introduced by 0febc381f3bb3d9073abeba3b7e725b8813723d8
and the regression failure at https://github.com/OpenXiangShan/XiangShan/actions/runs/2645135867.

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decode: move fusion decoder result Mux to rename (#1631)

This commit moves the fusion decoder to both decode and rename stage.

In the decode stage, fusion decoder determines whether the instructi

decode: move fusion decoder result Mux to rename (#1631)

This commit moves the fusion decoder to both decode and rename stage.

In the decode stage, fusion decoder determines whether the instruction
pairs can be fused. Valid bits of decode are not affected by fusion
decoder. This should fix the timing issues of rename.valid.

In the rename stage, some fields are updated according the result of
fusion decoder. This will bring a minor timing path to both valid and
other fields in uop in the rename stage. However, since freelist and
rat have worse timing. This should not cause timing issues.

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decode: parallel fusion decoder and rat read (#1588)

fix for chipsalliance/rocket-chip#2967 (#1562)

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic

Co-authored-by: Yinan Xu <[email protected]>

Bug fix on detection logic for addw fusion (#1276)

decode,fusion: optimize detection logic for addw and logic ops (#1262)

This commit optimizes instruction fusion detection logic for fused
addw{byte, bit, zexth, sexth}, mulw7, and logic{lsb, zexth}

decode,fusion: optimize detection logic for addw and logic ops (#1262)

This commit optimizes instruction fusion detection logic for fused
addw{byte, bit, zexth, sexth}, mulw7, and logic{lsb, zexth}
instructions.

Previously we use fuType and fuOpType from the normal decoder, and this
incurs a bad timing. Now we change the detection logic to use only the
raw instructions. Though the fused instruction still uses the
fuOpType from the normal decoder, there should be only serveral MUXes
left.

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backend: optimize aluOpType to 7 bits (#1061)

This commit optimizes ALUOpType to 7 bits. Alu timing will be checked
later.

We also apply some misc changes including:

* Move REVB, PACK, PACKH,

backend: optimize aluOpType to 7 bits (#1061)

This commit optimizes ALUOpType to 7 bits. Alu timing will be checked
later.

We also apply some misc changes including:

* Move REVB, PACK, PACKH, PACKW to ALU

* Add fused logicZexth, addwZext, addwSexth

* Add instruction fusion test cases to CI

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