feat(rv64): add Zimop extension support

* All MOP.R.n and MOP.RR.n only update rd with 0s. This would be changed when any MOP redefined by some other extensions.
* Define all MOP.R.n and MOP.RR.n se

feat(rv64): add Zimop extension support

* All MOP.R.n and MOP.RR.n only update rd with 0s. This would be changed when any MOP redefined by some other extensions.
* Define all MOP.R.n and MOP.RR.n seperated instruction name for future easier modification, since any one of MOP could be meaningful instruction in the future.
* If rd is not 0, mop instructions will convert to a move instruction, which move x0 to rd.
* If rd is 0, mop instructions will convert to a addi intruction, whose rs0 is x0 and imm is 0.

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Zvbb: support Zvbb instruction (#2686)

* support vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll
* bump yunsuan: support Zvbb

fix for chipsalliance/rocket-chip#2967 (#1562)

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic

Co-authored-by: Yinan Xu <[email protected]>

bku: fix sm4 instructions (#1263)

Svinval (#1055)

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure th

Svinval (#1055)

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure the software runs as follow:
begin instruction of svinval extension
svinval xxxx
svinval xxxx
...
end instruction of svinval extension

* Svinval: add an CSR to control it and some annotations

* Roq: fix assert bug of Svinval

* Svinval: fix svinval.vma's rs2 type
* make it reg instead of imm

* Svinval: change assert logic and fix bug
* fix the condition judging Svinval.vma instruction
* using doingSvinval in assert

* ci: add rv64mi-p-svinval to ci

* fix typo

* fix bug that lost ','

* when svinval disable, raise illegal instr excep

* CSR: mv svinval ctl to srnctl(1)

* rob: when excep, do not set dosvinval

* decode: when disable svinval, do not set flushpipe

* bump ready-to-run

Co-authored-by: ZhangZifei <[email protected]>

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mem: add Zicbom and Zicboz support (#1145)

Now we merge them for timing opt, unit test to be added later

riscv-crypto: support K extension (#1102)

* This commit add risc-v cryptography extension subset(zknd zkne zknh zksed zksh)
- Rename bmu to bku
- Add crypto instruction in Mdu -> bku
- Store imme

riscv-crypto: support K extension (#1102)

* This commit add risc-v cryptography extension subset(zknd zkne zknh zksed zksh)
- Rename bmu to bku
- Add crypto instruction in Mdu -> bku
- Store immediate into mdu RS

* ci: add riscv-crypto test

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backend: optimize aluOpType to 7 bits (#1061)

This commit optimizes ALUOpType to 7 bits. Alu timing will be checked
later.

We also apply some misc changes including:

* Move REVB, PACK, PACKH,

backend: optimize aluOpType to 7 bits (#1061)

This commit optimizes ALUOpType to 7 bits. Alu timing will be checked
later.

We also apply some misc changes including:

* Move REVB, PACK, PACKH, PACKW to ALU

* Add fused logicZexth, addwZext, addwSexth

* Add instruction fusion test cases to CI

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Bmu: support zbk* instruction (#1059)

* Bmu: support zbk* instructions

* ci: add zbk* instruction test

alu, decode: fix alu instruction and change instruction name (#1012)

* Alu: fix andn, orn, xnor

* Decode: change instruction name

Support RISC-V bitmanip extension v1.0 (#919)

* Add bitmanip v1.0 instructions into decede table
* Fix some instructions' name
* Add basic instructions into Alu
* Add clz, ctz, cpop, clmul Instru

Support RISC-V bitmanip extension v1.0 (#919)

* Add bitmanip v1.0 instructions into decede table
* Fix some instructions' name
* Add basic instructions into Alu
* Add clz, ctz, cpop, clmul Instruction into MulDivExeUnit

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misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

clean up deprecated decode codes

DecodeUnit: fix invalid_instr bug

DecodeUnit: Fill up decode frame.
DecodeUnitDiffTest: Add a diff-test with old Decoder.