timing(Vector,Decode): judge isComplex by inst encoding directly (#4066)

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(Backend): add support for Zacas extension

misc: remove assert temporarily

area(decode): move vecExceptionGen to complex docoder (#3961)

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

Decode: fix bug of numOfUop is 0 when vector instruction is illegalInst

build: purge chisel 3 and add deprecation check (#3250)

uopsplit: fix uop num for vfredosum instruction (#3230)

Decode: isComplex remove uopNum=/=1.U for fix timing (#3227)

rv64v: fix rfWen signal when writing x0 for vector instructions (#3107)

Merge branch 'master' into vlsu-tmp-master

rv64v: add new uop split method for segment indexed vload/vstore

numOfWB: make vector indexed instructions have dependencies between them

Co-authored-by: Ziyue Zhang <[email protected]>

rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

chisel: replace deprecated API

rv64v: fix uop spilt and mask generate for vlm

rv64v: fix vwred compute when lmul < 1

rv64v: fix uop split of vcompress instruction.

Co-authored-by: Guanghui Cheng <[email protected]>

rv64v: add f2v to remove all fs1 duplicate logic (#2613)

* rv64v: add f2v to remove all fs1 duplicate logic

* rv64v: use IntFPToVec module for i2v and f2v

rv64v: fix vxsat and vd compute for fixed-point instruction

rv64v: fix numOfWB compute

rv64v: fix vcpop and vfirst instructions

decode: refactor decode stage

* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in

decode: refactor decode stage

* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in decodeComp, the count of rename ready uops will be send to rename stage.

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rv64v：fix bug of load whole register (#2485)

* decode:fix decode of vs*r/vl*re*

Co-authored-by: Ziyue Zhang <[email protected]>

* UopQueue: fix bug in nfields and emul in store/load

rv64v：fix bug of load whole register (#2485)

* decode:fix decode of vs*r/vl*re*

Co-authored-by: Ziyue Zhang <[email protected]>

* UopQueue: fix bug in nfields and emul in store/load whole register

---------

Co-authored-by: Ziyue Zhang <[email protected]>

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rv64v: add write back num for indexed load/store (#2469)

* rv64v: add write back num for indexed load/store

* rv64v: fix write back num for vset