fix(uopsplit): set vector instructions never use simple split type (#4024)

* when use simple split type, instruction cannot send to complex decoder
and not do the exception check
* vs dirty is set

fix(uopsplit): set vector instructions never use simple split type (#4024)

* when use simple split type, instruction cannot send to complex decoder
and not do the exception check
* vs dirty is setted when split type is not simple

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fix(vnclip): use uimm instead of imm for vnclip_wi instructions (#3894)

Although the vs2 used by the vnclip instruction is signed, the immediate
number is unsigned.

feat(zvfh,zfh): add F16 support

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

zfhmin:add zfhmin extensions

*decode unit adds decoding of zfhmin extension related instructions
*Re exemplified the functional units for scalar fpcvt

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions exce

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions except above instructions, raise
illegal instruction exception
* when modify vstart, blockback and flushpipe

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rv64v: fix rfWen signal when writing x0 for vector instructions (#3107)

vset: use flushPipe with blockBack for vsetvl instructions

Decode: correctly specify fp inst's src num

backend: add scalar float function unit

float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>

Zvbb: support Zvbb instruction (#2686)

* support vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll
* bump yunsuan: support Zvbb

rv64v: fix decode for vwredsumu

rv64v: fix data merge for fp narrow convert instructions

rv64v: add vidiv module
* support vdiv, vdivu, vrem and vremu

rv64v: fix decode for vfclass instruction

rv64v: fix uop split type for vfmv

rv64v: add f2v to remove all fs1 duplicate logic (#2613)

* rv64v: add f2v to remove all fs1 duplicate logic

* rv64v: use IntFPToVec module for i2v and f2v

rv64v: fix special uimm compute for vmsleu, vmsgtu and vsaddu

rv64v: fix vmvnr when vl = 0

rv64v: fix vector move instruction

rv64v: fix vmv.s.x instruction

rv64v: support copy data directly use i2v
* also fix some bugs for vwadd.w and vrgather.vi

decode: fix uops of vset

decode: refactor decode stage

* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in

decode: refactor decode stage

* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in decodeComp, the count of rename ready uops will be send to rename stage.

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