fix(topdown): when instr fused, take it as NoStall (#4475)

feat: mark topdown, cycle and instr as critical perf counters (#4431)

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'de

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'dest after rename,
which cause stalls.

In this commit, we set src2 in uop0 and dest in uop1, avoiding stalls by
renaming.

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fix(vlbusytable): fix vlbusytable update (#4364)

submodule(utility), XSDebug: support collecting missing XSDebug (#4251)

Previous in PR#3982, we support collecting XSLogs to LogPerfEndpoint.
However with --enable-log, we should also collect some

submodule(utility), XSDebug: support collecting missing XSDebug (#4251)

Previous in PR#3982, we support collecting XSLogs to LogPerfEndpoint.
However with --enable-log, we should also collect some missing XSDebug.

This change move these missing XSDebug outside WhenContext, and add
WireInit to LogUtils' apply, to enable probing some subaccessed data,
like a vec elem with dynamic index.

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chore(dispatch): remove useless code and files (#4288)

feat(busytable): support eliminate old vd in new dispatch (#4198)

refactor(MemBlock): move MemBlock.scala from backend to mem (#4221)

timing(dispatch): fix timing of conserveFlowTotal

fix(newdispatch): uop with singlestep shouldn't be dispatched to iq

fix(dispatch): fix bug of hasException's instr send to iq

fix(dispatch): fix bug of index vld instr, each uop can be index vld instr

timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDispatch

feat(backend): NewDispatch