dispatch - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/dispatch

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
8757f860	06-Jul-2020	Yinan Xu <[email protected]>	dispatch2: fix src selection logic, use all previous Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala
53da9409	06-Jul-2020	Yinan Xu <[email protected]>	dispatch2,issuequeue: bug fix /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala
bc41f016	04-Jul-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/branch-age' into add-mul-div /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
f4553cb7	04-Jul-2020	Yinan Xu <[email protected]>	lsu: fix forward /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala
bfa4b2b4	04-Jul-2020	LinJiawei <[email protected]>	Cmp brTag /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
3e091f93	04-Jul-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into add-mul-div /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
6ddf5f35	04-Jul-2020	Yinan Xu <[email protected]>	exu: add mul, muldiv /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala
6d0f6fad	04-Jul-2020	LinJiawei <[email protected]>	Dispatch1: fix roq idx bug /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
ebfa1e8e	04-Jul-2020	LinJiawei <[email protected]>	Add log info /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
ab7d3e5f	03-Jul-2020	William Wang <[email protected]>	backend: redefine RoqIdxWidth /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/utils/MIMOQueue.scala /XiangShan/src/test/csrc/emu.h
d657848c	03-Jul-2020	Yinan Xu <[email protected]>	dispatch2: balanced alu arbiter /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/utils/MIMOQueue.scala /XiangShan/src/test/csrc/emu.h
3e60c717	02-Jul-2020	LinJiawei <[email protected]>	Dispatch: fix lsu ready /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
015fbae3	01-Jul-2020	Yinan Xu <[email protected]>	dispatch1: set valid when redirect /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala
39b8ec14	30-Jun-2020	Yinan Xu <[email protected]>	dispatch2: support imm and pc (will be deleted later) /XiangShan/.gitignore Dispatch2.scala
a2473afb	30-Jun-2020	Yinan Xu <[email protected]>	dispatch2: refactor regfile ports /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala Dispatch1.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
1b8dc8ff	29-Jun-2020	Yinan Xu <[email protected]>	dispatch2: fix src selection logic Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
43d38382	28-Jun-2020	William Wang <[email protected]>	dispatch: fix cancel and src pick logic /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala Dispatch1.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/test/csrc/difftest.cpp
81b87c92	28-Jun-2020	Yinan Xu <[email protected]>	dispatchqueue: add new line at end of file DispatchQueue.scala
55854ee1	28-Jun-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/dev-temp-lsu' into roq-writeback-log /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/stale_outputs_checked
819a0cbd	28-Jun-2020	Lemover <[email protected]>	Merge pull request #59 from RISCVERS/regfile-arbiter-5 writeback: allow write from all execution units /XiangShan/src/main/scala/xiangshan/Bundle.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
3ae16397	28-Jun-2020	Yinan Xu <[email protected]>	dispatch1: add init value for valid /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/log.cpp /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/top/XSSim.scala
052be50e	28-Jun-2020	Yinan Xu <[email protected]>	dispatch2: update src with imm or pc /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/log.cpp /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/top/XSSim.scala
a6ad6ca2	26-Jun-2020	Yinan Xu <[email protected]>	debug-log: add dispatch,busytable log Dispatch1.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
1dccb266	26-Jun-2020	Yinan Xu <[email protected]>	debug: add debug log /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala Dispatch1.scala Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/top/XSSim.scala
125414a1	24-Jun-2020	Yinan Xu <[email protected]>	dispatch: convert printf into XSInfo and XSDebug /XiangShan/Makefile /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVM.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZicsr.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala Dispatch1.scala Dispatch2.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala
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