area(EXU): add parameter `needCopySrc` in FuConfig (#4063)

feat(dbltrp) : add support for critical error (#3793)

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inva

NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inval`, `sfence.inval.ir`, `hfence.gvma`, `hinval.gvma`, `hfence.vvma` and `hinval.vvma`.

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NewCSR: add IMSIC

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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vtype: add valid signal for vsetvl instruction when calculate output

rv64v: fix the logic of writing vtype for vsetvl instruction

Merge branch 'master' into vlsu-tmp-master

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

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rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

exu: pipe frm

Backend: add some xsperf

rv64v: fix vxrm and frm connection for vector instructions

backend: implement uncertain latency exeUnit WbArbiter

Dispatch: split int dispatch to two regions

backend: add shouldBeInlined = false

fix merge error

backend: merge v2backend into backend