feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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area(exu): data signals only pipe once in exu

area(exu): ctrl signals only pipe once in exu

area(backend): only use startAddr in pcMem

area(Backend): merge pcMem and pcTargetMem

feat(dbltrp) : add support for critical error (#3793)

fix(csr): change connect0LatencyCtrlSingal to connectNonPipedCtrlSingal (#3647)

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inva

NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inval`, `sfence.inval.ir`, `hfence.gvma`, `hinval.gvma`, `hfence.vvma` and `hinval.vvma`.

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NewCSR: make XRET use redirect bundle to pass target instead of csr-rob direct connection

* TODO: remove isXRet signal from RobCSRIO.
* Add ftqIdx,ftqOffset in CSR Fu.
* XRet need not flushPipe

NewCSR: add IMSIC

FuConfig: split dataBits into destDataBits and srcDataBits for distinguish input and output data width

Exu: connect V0Wen VlWen

FuConfig: add writeV0Rf writeVlRf

vtype: add valid signal for vsetvl instruction when calculate output

rv64v: fix the logic of writing vtype for vsetvl instruction

Merge branch 'master' into vlsu-tmp-master

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

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Functionunit: move parameterized delay for fixtiming to latency field renamed as extralatency

Exu,FuncUnit,Vialufix: Add parameterized delay for fixtiming

rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

Parameters: remove write port configs for store

rv64v: fix vxrm and frm connection for vector instructions

backend: implement uncertain latency exeUnit WbArbiter

fix merge errors