fix(xtval): fix xtval when raise intr (#4307)

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is an GPAMem which
storages the whole 64-bit gpaddr, but it does not pass to CSR correctly,
due to incorrect width of trapPCGPA in module NewCSR and bundle
TrapEntryEventInput. This patch fixes this.

---------

Co-authored-by: ngc7331 <[email protected]>

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fix(xtval): fix selection of tval for trap

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.

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fix(Breakpoint): memory trigger set {m|s|vs}tval with faulting address (#3762)

* This commit fix the value of {m|s|vs}tval when load/store/atomic
trigger fire. The faulting address should be writte

fix(Breakpoint): memory trigger set {m|s|vs}tval with faulting address (#3762)

* This commit fix the value of {m|s|vs}tval when load/store/atomic
trigger fire. The faulting address should be written to tval.

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fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege

fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege.EX_BP writable in SMP Linux jobs.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(CSR): Add legalization code for mstatus.MPP, mnstatus.MNPP and dcsr.PRV (#3577)

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Backend: fix s/shvstvala, updata xtvala when EX_VI

Backend: support Shvstvala and Sstvala extension

fix the wrong condition of Mux1H about tval2 that makes wrong gpa written into htval or mtval2

CSR, RVH: fix the wrong val writen in htval when having igpf

ROB: clear flushPipe when the enq uop has exception (#3281)

CSR, RVH: fix the wrong stval and htval when igpf happens

NewCSR: update `mtinst` when trap entries M mode

NewCSR: set GVA=1 when hls insts trap load/store exceptions

NewCSR: mtval/htval should not hold lower 2 bits

NewCSR: Add Trigger CSR tcontrol

* add csr tcontrol.

* medeleg(EX_BP) hard-wired to 0. Parter 5.4 in debug spec. tcontrol is implemented. medeleg(3) is hard-wired to 0.

NewCSR: correct the produce of exception virtual address

* As specified by RISC-V specification, there are 3 different length of virtual address. They are `Bare`, `Sv39` and `Sv39x4`.
* The CSR mepc

NewCSR: correct the produce of exception virtual address

* As specified by RISC-V specification, there are 3 different length of virtual address. They are `Bare`, `Sv39` and `Sv39x4`.
* The CSR mepc and mtval use `Bare` address when the privilege mode is M mode or the satp.MODE is Bare.
* The CSR mepc and mtval use `Sv39` address when the privilege mode is S/U mode and the satp.MODE is Sv39 and when the privilege mode is VS/VU mode and the vsatp.MODE is Sv39.
* The CSR mepc and mtval use `Sv39x4` address when then privilege mode is VS/VU and the hgatp.MODE is Sv39x4 and the vsatp.MODE is Bare.
* The `Sv48` and `Sv48x4` support are provided partly in CSREvent for future usage.

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NewCSR: fix target pc of trap entry event

NewCSR: add CSR events