fix(csr): fix trap inst update when CSRR insts raise trap and remove useless io (#3620)

This PR fix trap inst update.
Because of CSRR inst is out of order insts, trap inst should select the
oldest

fix(csr): fix trap inst update when CSRR insts raise trap and remove useless io (#3620)

This PR fix trap inst update.
Because of CSRR inst is out of order insts, trap inst should select the
oldest trap inst when CSRR inst raise trap.

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Co-authored-by: Xuan Hu <[email protected]>

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CSR: store ftqInfo of csr inst to avoid wrong flush

CSR: fix trap inst update condition

* Never update trap inst if TrapInstMod already has valid inst.
* CSR illegal has higher priority to update trap inst, since the inst executed in CSR is order tha

CSR: fix trap inst update condition

* Never update trap inst if TrapInstMod already has valid inst.
* CSR illegal has higher priority to update trap inst, since the inst executed in CSR is order than all insts in decode stage

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Backend: only store 16 bits instr in tval when C extension EX_II occurs

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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